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/src/sys/contrib/dev/broadcom/brcm80211/brcmfmac/
H A Dchip.c18 #include "chip.h"
20 /* SOC Interconnect types (aka chip types) */
84 /* chip core base & ramsize */
223 struct brcmf_chip_priv *chip; member
256 ci = core->chip; in brcmf_chip_sb_iscoreup()
270 ci = core->chip; in brcmf_chip_ai_iscoreup()
286 ci = core->chip; in brcmf_chip_sb_coredisable()
356 ci = core->chip; in brcmf_chip_ai_coredisable()
391 ci = core->chip; in brcmf_chip_sb_resetcore()
442 ci = core->chip; in brcmf_chip_ai_resetcore()
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H A Dchip.h14 * struct brcmf_chip - chip level information.
16 * @chip: chip identifier.
17 * @chiprev: chip revision.
24 * @ramsize: amount of RAM on chip including retention.
25 * @srsize: amount of retention RAM on chip.
26 * @name: string representation of the chip identifier.
29 u32 chip; member
62 * @active: chip becomes active.
69 int (*reset)(void *ctx, struct brcmf_chip *chip);
70 int (*setup)(void *ctx, struct brcmf_chip *chip);
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/src/sys/contrib/device-tree/Bindings/mtd/
H A Dst,stm32-fmc2-nand.yaml41 $ref: raw-nand-chip.yaml
64 - description: Chip select 0 data
65 - description: Chip select 0 command
66 - description: Chip select 0 address space
67 - description: Chip select 1 data
68 - description: Chip select 1 command
69 - description: Chip select 1 address space
89 - description: Chip select 0 data
90 - description: Chip select 0 command
91 - description: Chip select 0 address space
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H A Dfsl-upm-nand.txt5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
55 /* Multi-chip NAND device */
/src/lib/libpmc/pmu-events/arch/powerpc/power8/
H A Dmemory.json5 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
6 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
11 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand …
12 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's memory on the sa…
23 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…
24 …"PublicDescription": "The processor's data cache was reloaded from the local chip's Memory due to …
35 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same No…
36 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on the same N…
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H A Dfrontend.json71 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instru…
72 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
89 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
90 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
95 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
96 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
101 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a di…
102 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a d…
107 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
108 …"PublicDescription": "The processor's Instruction cache was reloaded from another chip's memory on…
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H A Dmarked.json35 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
41 …eload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
47 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
53 … reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
59 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
65 …"BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Gr…
71 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
77 …"BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or G…
215 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
221 …"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked l…
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H A Dcache.json5 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
6 …oaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
11 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
12 …eloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
17 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
18 …"PublicDescription": "The processor's data cache was reloaded from another chip's L4 on a differen…
101 …"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to…
102 …"PublicDescription": "The processor's data cache was reloaded from the local chip's L4 cache due t…
107 …d either shared or modified data from another core's L2/L3 on a different chip (remote or distant)…
108 …d either shared or modified data from another core's L2/L3 on a different chip (remote or distant)…
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H A Dother.json23 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
24 …"PublicDescription": "Initial and Final Pump Scope and data sourced across this scope was chip pum…
36 … got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump w…
41 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
42 …urced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump w…
65 …ump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the origi…
66 …(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group…
71 …"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group…
72 …ope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all d…
377 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for either de…
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H A Dtranslation.json29 …e TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), …
35 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
89 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due t…
107 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)…
113 … TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side …
119 …the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
125 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
131 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
/src/contrib/ofed/libcxgb4/
H A Dt4_chip_type.h42 /* We code the Chelsio T4 Family "Chip Code" as a tuple:
44 * (Chip Version, Chip Revision)
48 * Chip Version: is T4, T5, etc.
49 * Chip Revision: is the FAB "spin" of the Chip Version.
75 static inline int is_t4(enum chip_type chip) in is_t4() argument
77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
80 static inline int is_t5(enum chip_type chip) in is_t5() argument
82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
85 static inline int is_t6(enum chip_type chip) in is_t6() argument
87 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
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/src/sys/contrib/dev/rtw88/
H A Dcoex.h330 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_init() local
332 chip->ops->coex_set_init(rtwdev); in rtw_coex_set_init()
338 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_ant_switch() local
340 if (!chip->ops->coex_set_ant_switch) in rtw_coex_set_ant_switch()
343 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); in rtw_coex_set_ant_switch()
348 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_fix() local
350 chip->ops->coex_set_gnt_fix(rtwdev); in rtw_coex_set_gnt_fix()
355 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_debug() local
357 chip->ops->coex_set_gnt_debug(rtwdev); in rtw_coex_set_gnt_debug()
362 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_rfe_type() local
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H A Dcoex.c16 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_next_rssi_state() local
17 u8 tol = chip->rssi_tolerance; in rtw_coex_next_rssi_state()
39 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_limited_tx() local
44 if (!chip->scbd_support) in rtw_coex_limited_tx()
368 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_write_scbd() local
373 if (!chip->scbd_support) in rtw_coex_write_scbd()
381 if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) { in rtw_coex_write_scbd()
403 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_read_scbd() local
405 if (!chip->scbd_support) in rtw_coex_read_scbd()
413 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_check_rfk() local
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H A Dmac.c169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
274 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_mac_power_switch() local
294 chip->id != RTW_CHIP_TYPE_8814A && in rtw_mac_power_switch()
311 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; in rtw_mac_power_switch()
315 if (chip->id == RTW_CHIP_TYPE_8822C || in rtw_mac_power_switch()
316 chip->id == RTW_CHIP_TYPE_8822B || in rtw_mac_power_switch()
317 chip->id == RTW_CHIP_TYPE_8821C) in rtw_mac_power_switch()
332 u8 sys_func_en = rtwdev->chip->sys_func_en; in __rtw_mac_init_system_cfg()
649 const struct rtw_chip_info *chip = rtwdev->chip; in download_firmware_to_mem() local
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H A Dphy.c162 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th; in rtw_phy_set_edcca_th()
177 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode() local
190 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; in rtw_phy_adaptivity_set_mode()
194 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; in rtw_phy_adaptivity_set_mode()
204 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_init() local
207 if (chip->ops->adaptivity_init) in rtw_phy_adaptivity_init()
208 chip->ops->adaptivity_init(rtwdev); in rtw_phy_adaptivity_init()
213 if (rtwdev->chip->ops->adaptivity) in rtw_phy_adaptivity()
214 rtwdev->chip->ops->adaptivity(rtwdev); in rtw_phy_adaptivity()
219 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_init() local
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/src/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dtranslation.json15 …ache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand loa…
25 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the …
35 …o the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
60 …the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), …
75 … TLB either shared or modified data from another core's L2/L3 on the same chip due to a instructio…
80 …ache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instructi…
95 …he was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand loa…
100 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same…
135 … reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
150 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)…
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H A Dmarked.json20 …aded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side …
25 …"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the sam…
30 …"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or mem…
60 …"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due…
70 … into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked dat…
95 …nto the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked dat…
100 … into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side …
120 …"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on …
130 …"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a…
145 …"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a…
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H A Dpipeline.json30 …aded either shared or modified data from another core's L2/L3 on the same chip due to a marked loa…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
80 …ed into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked dat…
90 …"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different…
95 …ed into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side …
135 …"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L…
160 …B either shared or modified data from another core's L2/L3 on a different chip (remote or distant)…
190 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
195 …"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data …
235 …eloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as…
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/src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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/src/share/man/man4/
H A Dahc.480 many chip-down motherboard configurations.
88 by a particular chip, may be disabled in a particular motherboard or card
92 .It Em "Chip" Ta "MIPS" Ta "Bus" Ta "MaxSync" Ta "MaxWidth" Ta "SCBs" Ta "Features"
112 Multi-function Twin Channel Device - Two controllers on one chip.
142 the chip for memory mapped I/O. The typical symptom of this problem is a
183 host adapter chip
187 host adapter chip
191 host adapter chip
195 host adapter chip
199 host adapter chip
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/src/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
36 - #address-cells: Number of cells required to define a chip select address
38 - #size-cells: Size of cells required to define a chip select address size
48 value specifies the analog chip address where user want to access
/src/sys/contrib/dev/rtw89/
H A Dphy.h566 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write8()
574 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write16()
582 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32()
590 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_set()
598 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_clr()
606 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_mask()
613 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read8()
620 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read16()
627 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read32()
635 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read32_mask()
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/src/lib/libpmc/pmu-events/arch/s390/cf_zec12/
H A Dextended.json89 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
90 …Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache witho…
95 "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
96 …ata cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cac…
125 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
126 … Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with …
131 "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
132 …ata cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cac…
143 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
144 …tion cache directory where the returned cache line was sourced from an On Chip Level-3 cache witho…
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/src/sys/dev/wbwd/
H A Dwbwd.c100 enum chips chip; member
117 * register as these might be different by chip.
126 enum chips chip; member
131 .chip = w83627hf,
136 .chip = w83627s,
141 .chip = w83697hf,
146 .chip = w83697ug,
151 .chip = w83637hf,
156 .chip = w83627thf,
161 .chip = w83687thf,
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/src/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
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