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/linux-6.8/drivers/i2c/busses/
Di2c-qcom-cci.c108 struct cci;
116 struct cci *cci; member
127 struct cci { struct
139 struct cci *cci = dev; in cci_isr() argument
143 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
144 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
145 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
148 complete(&cci->master[0].irq_complete); in cci_isr()
149 if (cci->master[1].master) in cci_isr()
150 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
/linux-6.8/Documentation/devicetree/bindings/i2c/
Dqcom,i2c-cci.yaml4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
28 - qcom,sc7280-cci
29 - qcom,sdm845-cci
30 - qcom,sm6350-cci
[all …]
/linux-6.8/Documentation/devicetree/bindings/arm/
Darm,cci-400.yaml4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
[all …]
Dcci-control-port.yaml4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
/linux-6.8/drivers/bus/
Darm-cci.c2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
/linux-6.8/Documentation/devicetree/bindings/interconnect/
Dmediatek,cci.yaml4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
35 - const: cci
44 Phandle of the regulator for CCI that provides the supply voltage.
48 Phandle of the regulator for sram of CCI that provides the supply
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
[all …]
/linux-6.8/drivers/usb/typec/ucsi/
Dtrace.c36 const char *ucsi_cci_str(u32 cci) in ucsi_cci_str() argument
38 if (UCSI_CCI_CONNECTOR(cci)) { in ucsi_cci_str()
39 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
41 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
45 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
47 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
Ducsi_acpi.c205 u32 cci; in ucsi_acpi_notify() local
208 ret = ua->ucsi->ops->read(ua->ucsi, UCSI_CCI, &cci, sizeof(cci)); in ucsi_acpi_notify()
212 if (UCSI_CCI_CONNECTOR(cci)) in ucsi_acpi_notify()
213 ucsi_connector_change(ua->ucsi, UCSI_CCI_CONNECTOR(cci)); in ucsi_acpi_notify()
215 if (cci & UCSI_CCI_ACK_COMPLETE && test_bit(ACK_PENDING, &ua->flags)) in ucsi_acpi_notify()
217 if (cci & UCSI_CCI_COMMAND_COMPLETE && in ucsi_acpi_notify()
Ducsi_glink.c221 u32 cci; in pmic_glink_ucsi_notify() local
224 ret = pmic_glink_ucsi_read(ucsi->ucsi, UCSI_CCI, &cci, sizeof(cci)); in pmic_glink_ucsi_notify()
226 dev_err(ucsi->dev, "failed to read CCI on notification\n"); in pmic_glink_ucsi_notify()
230 con_num = UCSI_CCI_CONNECTOR(cci); in pmic_glink_ucsi_notify()
246 if (ucsi->sync_pending && cci & UCSI_CCI_BUSY) { in pmic_glink_ucsi_notify()
250 (cci & (UCSI_CCI_ACK_COMPLETE | UCSI_CCI_COMMAND_COMPLETE))) { in pmic_glink_ucsi_notify()
/linux-6.8/drivers/perf/
DKconfig10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
Darm-cci.c2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
162 * Instead of an event id to monitor CCI cycles, a dedicated counter is
163 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
174 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
635 * Program the CCI PMU counters which have PERF_HES_ARCH set
749 * For all counters on the CCI-PMU, disable any 'enabled' counters,
788 * by the cci
834 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
[all …]
/linux-6.8/arch/arm/boot/dts/samsung/
Dexynos5422-cpus.dtsi62 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
101 cci-control-port = <&cci_control0>;
114 cci-control-port = <&cci_control1>;
127 cci-control-port = <&cci_control1>;
140 cci-control-port = <&cci_control1>;
153 cci-control-port = <&cci_control1>;
Dexynos5420-cpus.dtsi63 cci-control-port = <&cci_control1>;
75 cci-control-port = <&cci_control1>;
87 cci-control-port = <&cci_control1>;
99 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control0>;
123 cci-control-port = <&cci_control0>;
135 cci-control-port = <&cci_control0>;
147 cci-control-port = <&cci_control0>;
Dexynos5260.dtsi67 cci-control-port = <&cci_control1>;
74 cci-control-port = <&cci_control1>;
81 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
95 cci-control-port = <&cci_control0>;
102 cci-control-port = <&cci_control0>;
355 cci: cci@10f00000 { label
356 compatible = "arm,cci-400";
363 compatible = "arm,cci-400-ctrl-if";
369 compatible = "arm,cci-400-ctrl-if";
/linux-6.8/drivers/devfreq/
Dmtk-cci-devfreq.c173 /* switch the cci clock to intermediate clock source. */ in mtk_ccifreq_target()
176 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
183 dev_err(dev, "failed to set cci pll rate: %d\n", ret); in mtk_ccifreq_target()
188 /* switch the cci clock back to the original clock source. */ in mtk_ccifreq_target()
191 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
268 drv->cci_clk = devm_clk_get(dev, "cci"); in mtk_ccifreq_probe()
271 return dev_err_probe(dev, ret, "failed to get cci clk\n"); in mtk_ccifreq_probe()
427 { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
428 { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
443 MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
/linux-6.8/include/media/
Dv4l2-cci.h3 * MIPI Camera Control Interface (CCI) register access helpers.
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
38 * Private CCI register flags, for the use of drivers.
59 * cci_read() - Read a value from a single CCI register
72 * cci_write() - Write a value to a single CCI register
86 * a single CCI register
/linux-6.8/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt23 - mediatek,cci:
24 Used to confirm the link status between cpufreq and mediatek cci. Because
25 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
27 property to make sure mediatek cci is ready.
28 For details of mediatek cci, please refer to
29 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
/linux-6.8/arch/arm/boot/dts/mediatek/
Dmt7629.dtsi32 cci-control-port = <&cci_control2>;
40 cci-control-port = <&cci_control2>;
174 cci: cci@10390000 { label
175 compatible = "arm,cci-400";
182 compatible = "arm,cci-400-ctrl-if";
188 compatible = "arm,cci-400-ctrl-if";
194 compatible = "arm,cci-400-ctrl-if";
200 compatible = "arm,cci-400-pmu,r1";
/linux-6.8/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15_a7.dts42 cci-control-port = <&cci_control1>;
52 cci-control-port = <&cci_control1>;
62 cci-control-port = <&cci_control2>;
72 cci-control-port = <&cci_control2>;
82 cci-control-port = <&cci_control2>;
161 cci@2c090000 {
162 compatible = "arm,cci-400";
169 compatible = "arm,cci-400-ctrl-if";
175 compatible = "arm,cci-400-ctrl-if";
181 compatible = "arm,cci-400-pmu,r0";
/linux-6.8/arch/arm/mach-versatile/
Dplatsmp-vexpress.c28 * is to detect if the kernel can take over CCI ports in vexpress_smp_init_ops()
29 * control. Loop over possible CPUs and check if CCI in vexpress_smp_init_ops()
40 cci_node = of_parse_phandle(cpu_node, "cci-control-port", 0); in vexpress_smp_init_ops()
/linux-6.8/Documentation/driver-api/media/
Dv4l2-cci.rst3 V4L2 CCI kAPI
5 .. kernel-doc:: include/media/v4l2-cci.h
/linux-6.8/arch/arm64/boot/dts/mediatek/
Dmt6795.dtsi55 cci-control-port = <&cci_control2>;
64 cci-control-port = <&cci_control2>;
79 cci-control-port = <&cci_control2>;
94 cci-control-port = <&cci_control2>;
109 cci-control-port = <&cci_control1>;
124 cci-control-port = <&cci_control1>;
139 cci-control-port = <&cci_control1>;
154 cci-control-port = <&cci_control1>;
489 cci: cci@10390000 { label
490 compatible = "arm,cci-400";
[all …]
/linux-6.8/include/linux/
Darm-cci.h3 * CCI cache coherent interconnect support
14 #include <asm/arm-cci.h>
/linux-6.8/arch/arm/boot/dts/allwinner/
Dsun9i-a80.dtsi70 cci-control-port = <&cci_control0>;
79 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
97 cci-control-port = <&cci_control0>;
106 cci-control-port = <&cci_control1>;
115 cci-control-port = <&cci_control1>;
124 cci-control-port = <&cci_control1>;
133 cci-control-port = <&cci_control1>;
551 cci: cci@1c90000 { label
552 compatible = "arm,cci-400";
[all …]
/linux-6.8/drivers/media/v4l2-core/
Dv4l2-cci.c3 * MIPI Camera Control Interface (CCI) register access helpers.
17 #include <media/v4l2-cci.h>
194 MODULE_DESCRIPTION("MIPI Camera Control Interface (CCI) support");

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