| /linux-6.15/drivers/i2c/busses/ |
| D | i2c-qcom-cci.c | 108 struct cci;
116 struct cci *cci; member
126 struct cci { struct
138 struct cci *cci = dev; in cci_isr() argument
142 val = readl(cci->base + CCI_IRQ_STATUS_0); in cci_isr()
143 writel(val, cci->base + CCI_IRQ_CLEAR_0); in cci_isr()
144 writel(0x1, cci->base + CCI_IRQ_GLOBAL_CLEAR_CMD); in cci_isr()
147 complete(&cci->master[0].irq_complete); in cci_isr()
148 if (cci->master[1].master) in cci_isr()
149 complete(&cci->master[1].irq_complete); in cci_isr()
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/i2c/ |
| D | qcom,i2c-cci.yaml | 4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
28 - qcom,sc7280-cci
29 - qcom,sc8280xp-cci
30 - qcom,sdm670-cci
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
[all …]
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| D | cci-control-port.yaml | 4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
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| /linux-6.15/drivers/bus/ |
| D | arm-cci.c | 2 * CCI cache coherent interconnect driver
17 #include <linux/arm-cci.h>
49 {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
52 { .compatible = "arm,cci-500", },
53 { .compatible = "arm,cci-550", },
59 OF_DEV_AUXDATA("arm,cci-400-pmu", 0, NULL, &cci_ctrl_base),
60 OF_DEV_AUXDATA("arm,cci-400-pmu,r0", 0, NULL, &cci_ctrl_base),
61 OF_DEV_AUXDATA("arm,cci-400-pmu,r1", 0, NULL, &cci_ctrl_base),
62 OF_DEV_AUXDATA("arm,cci-500-pmu,r0", 0, NULL, &cci_ctrl_base),
63 OF_DEV_AUXDATA("arm,cci-550-pmu,r0", 0, NULL, &cci_ctrl_base),
[all …]
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| /linux-6.15/Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,cci.yaml | 4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
35 - const: cci
44 Phandle of the regulator for CCI that provides the supply voltage.
48 Phandle of the regulator for sram of CCI that provides the supply
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
[all …]
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| /linux-6.15/drivers/usb/typec/ucsi/ |
| D | cros_ec_ucsi.c | 79 static int cros_ucsi_read_cci(struct ucsi *ucsi, u32 *cci) in cros_ucsi_read_cci() argument
81 return cros_ucsi_read(ucsi, UCSI_CCI, cci, sizeof(*cci)); in cros_ucsi_read_cci()
108 static int cros_ucsi_sync_control(struct ucsi *ucsi, u64 cmd, u32 *cci, in cros_ucsi_sync_control() argument
114 ret = ucsi_sync_control_common(ucsi, cmd, cci, data, size); in cros_ucsi_sync_control()
117 /* EC may return -EBUSY if CCI.busy is set. in cros_ucsi_sync_control()
148 u32 cci; in cros_ucsi_work() local
150 if (cros_ucsi_read_cci(udata->ucsi, &cci)) in cros_ucsi_work()
153 ucsi_notify_common(udata->ucsi, cci); in cros_ucsi_work()
160 u32 cci; in cros_ucsi_write_timeout() local
163 if (cros_ucsi_read(udata->ucsi, UCSI_CCI, &cci, sizeof(cci))) { in cros_ucsi_write_timeout()
[all …]
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| D | trace.c | 36 const char *ucsi_cci_str(u32 cci) in ucsi_cci_str() argument
38 if (UCSI_CCI_CONNECTOR(cci)) { in ucsi_cci_str()
39 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
41 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
45 if (cci & UCSI_CCI_ACK_COMPLETE) in ucsi_cci_str()
47 if (cci & UCSI_CCI_COMMAND_COMPLETE) in ucsi_cci_str()
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| D | ucsi_acpi.c | 59 static int ucsi_acpi_read_cci(struct ucsi *ucsi, u32 *cci) in ucsi_acpi_read_cci() argument
63 memcpy(cci, ua->base + UCSI_CCI, sizeof(*cci)); in ucsi_acpi_read_cci()
68 static int ucsi_acpi_poll_cci(struct ucsi *ucsi, u32 *cci) in ucsi_acpi_poll_cci() argument
77 return ucsi_acpi_read_cci(ucsi, cci); in ucsi_acpi_poll_cci()
108 static int ucsi_gram_sync_control(struct ucsi *ucsi, u64 command, u32 *cci, in ucsi_gram_sync_control() argument
116 ret = ucsi_sync_control_common(ucsi, command, cci, val, len); in ucsi_gram_sync_control()
161 u32 cci; in ucsi_acpi_notify() local
164 ret = ua->ucsi->ops->read_cci(ua->ucsi, &cci); in ucsi_acpi_notify()
168 ucsi_notify_common(ua->ucsi, cci); in ucsi_acpi_notify()
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| D | ucsi_yoga_c630.c | 35 static int yoga_c630_ucsi_read_cci(struct ucsi *ucsi, u32 *cci) in yoga_c630_ucsi_read_cci() argument
45 memcpy(cci, buf, sizeof(*cci)); in yoga_c630_ucsi_read_cci()
87 u32 cci; in yoga_c630_ucsi_notify() local
97 ret = uec->ucsi->ops->read_cci(uec->ucsi, &cci); in yoga_c630_ucsi_notify()
101 ucsi_notify_common(uec->ucsi, cci); in yoga_c630_ucsi_notify()
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| D | ucsi.c | 39 void ucsi_notify_common(struct ucsi *ucsi, u32 cci) in ucsi_notify_common() argument
41 /* Ignore bogus data in CCI if busy indicator is set. */ in ucsi_notify_common()
42 if (cci & UCSI_CCI_BUSY) in ucsi_notify_common()
45 if (UCSI_CCI_CONNECTOR(cci)) in ucsi_notify_common()
46 ucsi_connector_change(ucsi, UCSI_CCI_CONNECTOR(cci)); in ucsi_notify_common()
48 if (cci & UCSI_CCI_ACK_COMPLETE && in ucsi_notify_common()
52 if (cci & UCSI_CCI_COMMAND_COMPLETE && in ucsi_notify_common()
58 int ucsi_sync_control_common(struct ucsi *ucsi, u64 command, u32 *cci, in ucsi_sync_control_common() argument
84 if (!ret && cci) in ucsi_sync_control_common()
85 ret = ucsi->ops->read_cci(ucsi, cci); in ucsi_sync_control_common()
[all …]
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| D | ucsi_glink.c | 121 static int pmic_glink_ucsi_read_cci(struct ucsi *ucsi, u32 *cci) in pmic_glink_ucsi_read_cci() argument
123 return pmic_glink_ucsi_read(ucsi, UCSI_CCI, cci, sizeof(*cci)); in pmic_glink_ucsi_read_cci()
241 u32 cci; in pmic_glink_ucsi_notify() local
244 ret = pmic_glink_ucsi_read(ucsi->ucsi, UCSI_CCI, &cci, sizeof(cci)); in pmic_glink_ucsi_notify()
246 dev_err(ucsi->dev, "failed to read CCI on notification\n"); in pmic_glink_ucsi_notify()
250 ucsi_notify_common(ucsi->ucsi, cci); in pmic_glink_ucsi_notify()
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| D | ucsi_ccg.c | 197 __le32 cci; member
230 * This spinlock protects op_data which includes CCI and MESSAGE_IN that
318 static int ccg_op_region_update(struct ucsi_ccg *uc, u32 cci) in ccg_op_region_update() argument
328 if (UCSI_CCI_LENGTH(cci)) { in ccg_op_region_update()
338 data->cci = cpu_to_le32(cci); in ccg_op_region_update()
339 if (UCSI_CCI_LENGTH(cci)) in ccg_op_region_update()
567 static int ucsi_ccg_read_cci(struct ucsi *ucsi, u32 *cci) in ucsi_ccg_read_cci() argument
572 *cci = uc->op_data.cci; in ucsi_ccg_read_cci()
595 * UCSI may read CCI instantly after async_control, in ucsi_ccg_async_control()
596 * clear CCI to avoid caller getting wrong data before we get CCI from ISR in ucsi_ccg_async_control()
[all …]
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| /linux-6.15/drivers/media/i2c/ |
| D | imx283.c | 32 #include <media/v4l2-cci.h>
549 struct regmap *cci; member
738 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL); in imx283_update_test_pattern()
740 ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT, in imx283_update_test_pattern()
745 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, in imx283_update_test_pattern()
801 ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL); in imx283_set_ctrl()
809 ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL); in imx283_set_ctrl()
816 ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL); in imx283_set_ctrl()
820 ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL); in imx283_set_ctrl()
824 ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL); in imx283_set_ctrl()
[all …]
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| D | imx335.c | 16 #include <media/v4l2-cci.h>
179 * @cci: CCI register map
202 struct regmap *cci; member
480 cci_write(imx335->cci, IMX335_REG_HOLD, 1, &ret); in imx335_update_exp_gain()
481 cci_write(imx335->cci, IMX335_REG_VMAX, lpfr, &ret); in imx335_update_exp_gain()
482 cci_write(imx335->cci, IMX335_REG_SHUTTER, shutter, &ret); in imx335_update_exp_gain()
483 cci_write(imx335->cci, IMX335_REG_GAIN, gain, &ret); in imx335_update_exp_gain()
488 ret_hold = cci_write(imx335->cci, IMX335_REG_HOLD, 0, NULL); in imx335_update_exp_gain()
512 cci_write(imx335->cci, IMX335_REG_TPG, in imx335_update_test_pattern()
515 cci_multi_reg_write(imx335->cci, tpg_enable_regs, in imx335_update_test_pattern()
[all …]
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| /linux-6.15/drivers/perf/ |
| D | Kconfig | 10 tristate "ARM CCI PMU driver"
14 Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
35 internal events to the CCI.
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| D | arm-cci.c | 2 // CCI Cache Coherent Interconnect PMU driver
6 #include <linux/arm-cci.h>
16 #define DRIVER_NAME "ARM-CCI PMU"
160 * Instead of an event id to monitor CCI cycles, a dedicated counter is
161 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
172 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
633 * Program the CCI PMU counters which have PERF_HES_ARCH set
739 * For all counters on the CCI-PMU, disable any 'enabled' counters,
778 * by the cci
824 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
[all …]
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| /linux-6.15/arch/arm/boot/dts/samsung/ |
| D | exynos5422-cpus.dtsi | 62 cci-control-port = <&cci_control0>;
75 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
101 cci-control-port = <&cci_control0>;
114 cci-control-port = <&cci_control1>;
127 cci-control-port = <&cci_control1>;
140 cci-control-port = <&cci_control1>;
153 cci-control-port = <&cci_control1>;
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| D | exynos5420-cpus.dtsi | 63 cci-control-port = <&cci_control1>;
75 cci-control-port = <&cci_control1>;
87 cci-control-port = <&cci_control1>;
99 cci-control-port = <&cci_control1>;
111 cci-control-port = <&cci_control0>;
123 cci-control-port = <&cci_control0>;
135 cci-control-port = <&cci_control0>;
147 cci-control-port = <&cci_control0>;
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| D | exynos5260.dtsi | 67 cci-control-port = <&cci_control1>;
74 cci-control-port = <&cci_control1>;
81 cci-control-port = <&cci_control0>;
88 cci-control-port = <&cci_control0>;
95 cci-control-port = <&cci_control0>;
102 cci-control-port = <&cci_control0>;
355 cci: cci@10f00000 { label
356 compatible = "arm,cci-400";
363 compatible = "arm,cci-400-ctrl-if";
369 compatible = "arm,cci-400-ctrl-if";
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| /linux-6.15/drivers/devfreq/ |
| D | mtk-cci-devfreq.c | 173 /* switch the cci clock to intermediate clock source. */ in mtk_ccifreq_target()
176 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
183 dev_err(dev, "failed to set cci pll rate: %d\n", ret); in mtk_ccifreq_target()
188 /* switch the cci clock back to the original clock source. */ in mtk_ccifreq_target()
191 dev_err(dev, "failed to re-parent cci clock\n"); in mtk_ccifreq_target()
268 drv->cci_clk = devm_clk_get(dev, "cci"); in mtk_ccifreq_probe()
271 return dev_err_probe(dev, ret, "failed to get cci clk\n"); in mtk_ccifreq_probe()
425 { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
426 { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
441 MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
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| /linux-6.15/include/media/ |
| D | v4l2-cci.h | 3 * MIPI Camera Control Interface (CCI) register access helpers.
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
38 * Private CCI register flags, for the use of drivers.
59 * cci_read() - Read a value from a single CCI register
72 * cci_write() - Write a value to a single CCI register
86 * a single CCI register
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| /linux-6.15/Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 23 - mediatek,cci:
24 Used to confirm the link status between cpufreq and mediatek cci. Because
25 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
27 property to make sure mediatek cci is ready.
28 For details of mediatek cci, please refer to
29 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
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| /linux-6.15/arch/arm/boot/dts/mediatek/ |
| D | mt7629.dtsi | 32 cci-control-port = <&cci_control2>;
40 cci-control-port = <&cci_control2>;
174 cci: cci@10390000 { label
175 compatible = "arm,cci-400";
182 compatible = "arm,cci-400-ctrl-if";
188 compatible = "arm,cci-400-ctrl-if";
194 compatible = "arm,cci-400-ctrl-if";
200 compatible = "arm,cci-400-pmu,r1";
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| /linux-6.15/arch/arm/boot/dts/arm/ |
| D | vexpress-v2p-ca15_a7.dts | 42 cci-control-port = <&cci_control1>;
52 cci-control-port = <&cci_control1>;
62 cci-control-port = <&cci_control2>;
72 cci-control-port = <&cci_control2>;
82 cci-control-port = <&cci_control2>;
161 cci@2c090000 {
162 compatible = "arm,cci-400";
169 compatible = "arm,cci-400-ctrl-if";
175 compatible = "arm,cci-400-ctrl-if";
181 compatible = "arm,cci-400-pmu,r0";
|