Searched +full:cbop +full:- +full:block +full:- +full:size (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: RISC-V CPUs10 - Paul Walmsley <paul.walmsley@sifive.com>11 - Palmer Dabbelt <palmer@sifive.com>12 - Conor Dooley <conor@kernel.org>15 This document uses some terminology common to the RISC-V community19 mandated by the RISC-V ISA: a PC and some registers. This27 - $ref: /schemas/cpu.yaml#[all …]
1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)6 * Copyright (C) 2000 - 2023, Intel Corp.51 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */59 * All tables must be byte-packed to match the ACPI specification, since69 * essentially useless for dealing with packed data in on-disk formats or78 * AEST - Arm Error Source Table89 /* Common Subtable header - one per Node Structure (Subtable) */246 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface266 * APMT - ARM Performance Monitoring Unit Table[all …]