Searched +full:cbop +full:- +full:block +full:- +full:size (Results 1 – 3 of 3) sorted by relevance
| /linux-6.15/arch/riscv/boot/dts/spacemit/ |
| D | k1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <24000000>;
18 cpu-map {
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
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| /linux-6.15/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /linux-6.15/include/acpi/ |
| D | actbl2.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
6 * Copyright (C) 2000 - 2023, Intel Corp.
52 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
60 * All tables must be byte-packed to match the ACPI specification, since
70 * essentially useless for dealing with packed data in on-disk formats or
79 * AEST - Arm Error Source Table
90 /* Common Subtable header - one per Node Structure (Subtable) */
323 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
343 * APMT - ARM Performance Monitoring Unit Table
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