Searched +full:cbom +full:- +full:block +full:- +full:size (Results 1 – 5 of 5) sorted by relevance
| /linux-6.8/arch/riscv/mm/ |
| D | cacheflush.c | 1 // SPDX-License-Identifier: GPL-2.0-only
32 * Performs an icache flush for the given MM context. RISC-V has no direct
36 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
49 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
62 if (mm == current->active_mm && local) { in flush_icache_mm()
89 if (!test_bit(PG_dcache_clean, &folio->flags)) { in flush_icache_pte()
91 set_bit(PG_dcache_clean, &folio->flags); in flush_icache_pte()
134 /* set block-size for cbom and/or cboz extension if available */ in riscv_init_cbo_blocksizes()
135 cbo_get_block_size(node, "riscv,cbom-block-size", in riscv_init_cbo_blocksizes()
137 cbo_get_block_size(node, "riscv,cboz-block-size", in riscv_init_cbo_blocksizes()
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| D | dma-noncoherent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V specific functions to support DMA for non-coherent devices
8 #include <linux/dma-direct.h>
9 #include <linux/dma-map-ops.h>
12 #include <asm/dma-noncoherent.h>
18 static inline void arch_dma_cache_wback(phys_addr_t paddr, size_t size) in arch_dma_cache_wback() argument
24 noncoherent_cache_ops.wback(paddr, size); in arch_dma_cache_wback()
28 ALT_CMO_OP(CLEAN, vaddr, size, riscv_cbom_block_size); in arch_dma_cache_wback()
31 static inline void arch_dma_cache_inv(phys_addr_t paddr, size_t size) in arch_dma_cache_inv() argument
37 noncoherent_cache_ops.inv(paddr, size); in arch_dma_cache_inv()
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| /linux-6.8/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /linux-6.8/arch/riscv/kernel/ |
| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "copy-unaligned.h"
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
37 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
44 /* Per-cpu ISA extensions. */
53 * riscv_isa_extension_base() - Get base extension word
69 * __riscv_isa_extension_available() - Check whether given extension
94 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
97 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
103 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_isa_extension_check()
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| /linux-6.8/include/acpi/ |
| D | actbl2.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions (tables not in ACPI spec)
6 * Copyright (C) 2000 - 2023, Intel Corp.
51 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
59 * All tables must be byte-packed to match the ACPI specification, since
69 * essentially useless for dealing with packed data in on-disk formats or
78 * AEST - Arm Error Source Table
89 /* Common Subtable header - one per Node Structure (Subtable) */
246 * AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
266 * APMT - ARM Performance Monitoring Unit Table
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