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/linux-5.10/arch/mips/kernel/
Dirq-gt641xx.c22 u32 cause; in ack_gt641xx_irq() local
25 cause = GT_READ(GT_INTRCAUSE_OFS); in ack_gt641xx_irq()
26 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); in ack_gt641xx_irq()
27 GT_WRITE(GT_INTRCAUSE_OFS, cause); in ack_gt641xx_irq()
46 u32 cause, mask; in mask_ack_gt641xx_irq() local
53 cause = GT_READ(GT_INTRCAUSE_OFS); in mask_ack_gt641xx_irq()
54 cause &= ~GT641XX_IRQ_TO_BIT(d->irq); in mask_ack_gt641xx_irq()
55 GT_WRITE(GT_INTRCAUSE_OFS, cause); in mask_ack_gt641xx_irq()
81 u32 cause, mask; in gt641xx_irq_dispatch() local
84 cause = GT_READ(GT_INTRCAUSE_OFS); in gt641xx_irq_dispatch()
[all …]
/linux-5.10/arch/mips/kvm/
Dtrap_emul.c47 u32 cause = vcpu->arch.host_cp0_cause; in kvm_trap_emul_no_handler() local
48 u32 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; in kvm_trap_emul_no_handler()
55 if (cause & CAUSEF_BD) in kvm_trap_emul_no_handler()
71 u32 cause = vcpu->arch.host_cp0_cause; in kvm_trap_emul_handle_cop_unusable() local
75 if (((cause & CAUSEF_CE) >> CAUSEB_CE) == 1) { in kvm_trap_emul_handle_cop_unusable()
83 er = kvm_mips_emulate_fpu_exc(cause, opc, vcpu); in kvm_trap_emul_handle_cop_unusable()
90 er = kvm_mips_emulate_inst(cause, opc, vcpu); in kvm_trap_emul_handle_cop_unusable()
118 static int kvm_mips_bad_load(u32 cause, u32 *opc, struct kvm_vcpu *vcpu) in kvm_mips_bad_load() argument
131 if (cause & CAUSEF_BD) in kvm_mips_bad_load()
140 er = kvm_mips_emulate_load(inst, cause, vcpu); in kvm_mips_bad_load()
[all …]
Dinterrupt.c37 * Cause bits to reflect the pending timer interrupt, in kvm_mips_queue_timer_int_cb()
60 * Cause bits to reflect the pending IO interrupt, in kvm_mips_queue_io_int_cb()
79 u32 cause) in kvm_mips_irq_deliver_cb() argument
105 if (cause & CAUSEF_BD) in kvm_mips_irq_deliver_cb()
132 u32 cause) in kvm_mips_irq_clear_cb() argument
137 void kvm_mips_deliver_interrupts(struct kvm_vcpu *vcpu, u32 cause) in kvm_mips_deliver_interrupts() argument
148 if (kvm_mips_callbacks->irq_clear(vcpu, priority, cause)) { in kvm_mips_deliver_interrupts()
160 if (kvm_mips_callbacks->irq_deliver(vcpu, priority, cause)) { in kvm_mips_deliver_interrupts()
Dvz.c258 u32 cause) in kvm_vz_irq_deliver_cb() argument
287 u32 cause) in kvm_vz_irq_clear_cb() argument
295 * Call to kvm_write_c0_guest_compare() clears Cause.TI in in kvm_vz_irq_clear_cb()
297 * Cause.IP[IPTI] if GuestCtl2 virtual interrupt register not in kvm_vz_irq_clear_cb()
361 * @cause: CP0_Cause register to restore.
367 u32 cause) in _kvm_vz_restore_stimer() argument
376 write_gc0_cause(cause); in _kvm_vz_restore_stimer()
383 * @cause: CP0_Cause register to restore.
385 * Restore hard timer Guest.Count & Guest.Cause taking care to preserve the
389 u32 compare, u32 cause) in _kvm_vz_restore_htimer() argument
[all …]
Demulate.c244 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause) in update_pc() argument
248 if (cause & CAUSEF_BD) { in update_pc()
702 u32 cause; in kvm_mips_write_compare() local
742 cause = kvm_read_c0_guest_cause(cop0); in kvm_mips_write_compare()
752 if (!ack && cause & CAUSEF_TI) in kvm_mips_write_compare()
753 kvm_write_c0_guest_cause(cop0, cause); in kvm_mips_write_compare()
1264 u32 *opc, u32 cause, in kvm_mips_emulate_CP0() argument
1277 er = update_pc(vcpu, cause); in kvm_mips_emulate_CP0()
1598 u32 cause, in kvm_mips_emulate_store() argument
1614 er = update_pc(vcpu, cause); in kvm_mips_emulate_store()
[all …]
/linux-5.10/arch/mips/bcm47xx/
Dirq.c36 u32 cause; in plat_irq_dispatch() local
38 cause = read_c0_cause() & read_c0_status() & CAUSEF_IP; in plat_irq_dispatch()
40 clear_c0_status(cause); in plat_irq_dispatch()
42 if (cause & CAUSEF_IP7) in plat_irq_dispatch()
44 if (cause & CAUSEF_IP2) in plat_irq_dispatch()
46 if (cause & CAUSEF_IP3) in plat_irq_dispatch()
48 if (cause & CAUSEF_IP4) in plat_irq_dispatch()
50 if (cause & CAUSEF_IP5) in plat_irq_dispatch()
52 if (cause & CAUSEF_IP6) in plat_irq_dispatch()
/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/
Dvirtual-memory.json5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
20 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
31 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
42 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
88 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
97 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
112 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
119 … "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
[all …]
/linux-5.10/tools/perf/pmu-events/arch/x86/broadwell/
Dvirtual-memory.json3 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
10 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
14 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
25 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
36 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
91 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
95 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
102 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
106 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
117 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
[all …]
/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellde/
Dvirtual-memory.json5 "BriefDescription": "Load misses in all DTLB levels that cause page walks",
9 …"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of an…
20 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
31 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
42 …"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page…
88 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
97 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
101 …"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of a…
112 …"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed pag…
119 … "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
[all …]
/linux-5.10/tools/perf/pmu-events/arch/x86/sandybridge/
Dvirtual-memory.json8 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
17 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
31 …d operations that miss the first DTLB level but hit the second and do not cause any page walks. Th…
37 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
46 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
55 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
73 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
91 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
100 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
119 …": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
/linux-5.10/tools/perf/pmu-events/arch/x86/jaketown/
Dvirtual-memory.json26 "BriefDescription": "Misses at all ITLB levels that cause page walks.",
35 "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
54 …": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
63 "BriefDescription": "Load misses in all DTLB levels that cause page walks.",
72 "BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
86 …d operations that miss the first DTLB level but hit the second and do not cause any page walks. Th…
92 …: "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
101 "BriefDescription": "Store misses in all DTLB levels that cause page walks.",
110 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
128 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
/linux-5.10/tools/perf/pmu-events/arch/x86/ivybridge/
Dvirtual-memory.json3 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
48 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
58 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
72 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
78 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
97 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
101 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
107 "BriefDescription": "Misses at all ITLB levels that cause page walks",
111 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
117 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
[all …]
/linux-5.10/arch/riscv/mm/
Dfault.c72 /* User mode accesses just cause a SIGSEGV */ in bad_area()
91 /* User mode accesses just cause a SIGSEGV */ in vmalloc_fault()
161 static inline bool access_error(unsigned long cause, struct vm_area_struct *vma) in access_error() argument
163 switch (cause) { in access_error()
180 panic("%s: unhandled cause %lu", __func__, cause); in access_error()
194 unsigned long addr, cause; in do_page_fault() local
199 cause = regs->cause; in do_page_fault()
237 if (cause == EXC_STORE_PAGE_FAULT) in do_page_fault()
239 else if (cause == EXC_INST_PAGE_FAULT) in do_page_fault()
266 if (unlikely(access_error(cause, vma))) { in do_page_fault()
/linux-5.10/tools/perf/pmu-events/arch/x86/ivytown/
Dvirtual-memory.json3 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
66 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
76 "BriefDescription": "Store misses in all DTLB levels that cause completed page walks",
90 …: "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
96 …": "Store operations that miss the first TLB level but hit the second and do not cause page walks",
115 …": "Load operations that miss the first DTLB level but hit the second and do not cause page walks",
119 "PublicDescription": "Misses in all ITLB levels that cause page walks.",
125 "BriefDescription": "Misses at all ITLB levels that cause page walks",
129 "PublicDescription": "Misses in all ITLB levels that cause completed page walks.",
135 "BriefDescription": "Misses in all ITLB levels that cause completed page walks",
[all …]
/linux-5.10/drivers/net/ethernet/chelsio/cxgb/
Dsubr.c196 u32 cause = readl(adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler() local
199 if (cause & (1 << p)) { in fpga_phy_intr_handler()
206 writel(cause, adapter->regs + FPGA_GMAC_ADDR_INTERRUPT_CAUSE); in fpga_phy_intr_handler()
215 u32 cause = readl(adapter->regs + A_PL_CAUSE); in fpga_slow_intr() local
217 cause &= ~F_PL_INTR_SGE_DATA; in fpga_slow_intr()
218 if (cause & F_PL_INTR_SGE_ERR) in fpga_slow_intr()
221 if (cause & FPGA_PCIX_INTERRUPT_GMAC) in fpga_slow_intr()
224 if (cause & FPGA_PCIX_INTERRUPT_TP) { in fpga_slow_intr()
234 if (cause & FPGA_PCIX_INTERRUPT_PCIX) in fpga_slow_intr()
238 if (cause) in fpga_slow_intr()
[all …]
/linux-5.10/security/integrity/ima/
Dima_appraise.c229 enum integrity_status *status, const char **cause) in xattr_verify() argument
240 *cause = "IMA-signature-required"; in xattr_verify()
257 *cause = "invalid-hash"; in xattr_verify()
282 *cause = "invalid-signature"; in xattr_verify()
290 *cause = "unknown-ima-data"; in xattr_verify()
305 enum integrity_status *status, const char **cause) in modsig_verify() argument
315 *cause = "invalid-signature"; in modsig_verify()
371 const char *cause = "unknown"; in ima_appraise_measurement() local
387 cause = iint->flags & IMA_DIGSIG_REQUIRED ? in ima_appraise_measurement()
411 cause = "missing-HMAC"; in ima_appraise_measurement()
[all …]
/linux-5.10/drivers/edac/
Dmv64x60_edac.c33 u32 cause; in mv64x60_pci_check() local
35 cause = readl(pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); in mv64x60_pci_check()
36 if (!cause) in mv64x60_pci_check()
40 printk(KERN_ERR "Cause register: 0x%08x\n", cause); in mv64x60_pci_check()
49 writel(~cause, pdata->pci_vbase + MV64X60_PCI_ERROR_CAUSE); in mv64x60_pci_check()
51 if (cause & MV64X60_PCI_PE_MASK) in mv64x60_pci_check()
54 if (!(cause & MV64X60_PCI_PE_MASK)) in mv64x60_pci_check()
234 u32 cause; in mv64x60_sram_check() local
236 cause = readl(pdata->sram_vbase + MV64X60_SRAM_ERR_CAUSE); in mv64x60_sram_check()
237 if (!cause) in mv64x60_sram_check()
[all …]
/linux-5.10/drivers/dma/idxd/
Dirq.c62 u32 cause, val = 0; in idxd_misc_thread() local
66 cause = ioread32(idxd->reg_base + IDXD_INTCAUSE_OFFSET); in idxd_misc_thread()
67 iowrite32(cause, idxd->reg_base + IDXD_INTCAUSE_OFFSET); in idxd_misc_thread()
69 if (cause & IDXD_INTC_ERR) { in idxd_misc_thread()
102 if (cause & IDXD_INTC_CMD) { in idxd_misc_thread()
107 if (cause & IDXD_INTC_OCCUPY) { in idxd_misc_thread()
112 if (cause & IDXD_INTC_PERFMON_OVFL) { in idxd_misc_thread()
120 val ^= cause; in idxd_misc_thread()
122 dev_warn_once(dev, "Unexpected interrupt cause bits set: %#x\n", in idxd_misc_thread()
/linux-5.10/arch/nios2/kernel/
Dtraps.c94 * down the cause of the crash will be able to figure in show_stack()
127 asmlinkage void handle_unaligned_c(struct pt_regs *fp, int cause) in handle_unaligned_c() argument
131 cause >>= 2; in handle_unaligned_c()
141 pr_alert(" cause %d\n", cause); in handle_unaligned_c()
173 asmlinkage void unhandled_exception(struct pt_regs *regs, int cause) in unhandled_exception() argument
177 cause /= 4; in unhandled_exception()
180 cause, user_mode(regs) ? "user" : "kernel", addr); in unhandled_exception()
/linux-5.10/security/integrity/
Dintegrity_audit.c30 const char *cause, int result, int audit_info) in integrity_audit_msg() argument
32 integrity_audit_message(audit_msgno, inode, fname, op, cause, in integrity_audit_msg()
38 const char *cause, int result, int audit_info, in integrity_audit_message() argument
54 audit_log_format(ab, " op=%s cause=%s comm=", op, cause); in integrity_audit_message()
/linux-5.10/drivers/staging/rtl8723bs/include/
Drtw_ioctl.h63 #define NDIS_STATUS_DEST_OUT_OF_ORDER ((uint)0xC0010024L) /* cause 27 */
64 #define NDIS_STATUS_VC_NOT_AVAILABLE ((uint)0xC0010025L) /* cause 35, 45 */
65 #define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((uint)0xC0010026L) /* cause 37 */
66 #define NDIS_STATUS_INCOMPATABLE_QOS ((uint)0xC0010027L) /* cause 49 */
67 #define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((uint)0xC0010028L) /* cause 93 */
68 #define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((uint)0xC0010029L) /* cause 3 */
/linux-5.10/drivers/irqchip/
Dirq-riscv-intc.c24 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq() local
26 if (unlikely(cause >= BITS_PER_LONG)) in riscv_intc_irq()
27 panic("unexpected interrupt cause"); in riscv_intc_irq()
29 switch (cause) { in riscv_intc_irq()
40 handle_domain_irq(intc_domain, cause, regs); in riscv_intc_irq()
/linux-5.10/drivers/atm/
DuPD98402.h16 #define uPD98402_PICR 0x02 /* PHY Interrupt Cause Register */
18 #define uPD98402_ACR 0x04 /* Alarm Cause Register */
19 #define uPD98402_ACMR 0x05 /* Alarm Cause Mask Register */
20 #define uPD98402_PCR 0x06 /* Performance Cause Register */
21 #define uPD98402_PCMR 0x07 /* Performance Cause Mask Register */
22 #define uPD98402_IACM 0x08 /* Internal Alarm Cause Mask Register */
30 #define uPD98402_PCOCR 0x10 /* Perf. Counter Overflow Cause Reg */
/linux-5.10/arch/mips/include/asm/
Dkvm_host.h736 __BUILD_KVM_RW_HW(cause, 32, MIPS_CP0_CAUSE, 0)
760 /* Cause can be modified asynchronously from hardirq hrtimer callback */
761 __BUILD_KVM_ATOMIC_HW(cause, 32, MIPS_CP0_CAUSE, 0)
835 u32 cause);
837 u32 cause);
900 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
979 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
994 u32 cause = vcpu->host_cp0_cause; in kvm_is_ifetch_fault() local
1004 if ((cause & CAUSEF_BD) && badvaddr - epc <= 4) in kvm_is_ifetch_fault()
1010 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
[all …]
/linux-5.10/arch/mips/sgi-ip30/
Dip30-irq.c45 u64 pending, mask, cause, error_irqs, err_reg; in ip30_error_irq() local
51 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
65 * If we also have a cause value, then something happened, so loop in ip30_error_irq()
67 * and print the value of the HEART cause register. This is really in ip30_error_irq()
71 * Refer to heart.h for the HC_* macros to work out the cause in ip30_error_irq()
74 if (cause) { in ip30_error_irq()
75 pr_alert("IP30: CPU%d: HEART ATTACK! ISR = 0x%.16llx, IMR = 0x%.16llx, CAUSE = 0x%.16llx\n", in ip30_error_irq()
76 cpu, pending, mask, cause); in ip30_error_irq()
78 if (cause & HC_COR_MEM_ERR) { in ip30_error_irq()

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