| /qemu/docs/ |
| H A D | pcie_pci_bridge.txt | 35 Red Hat vendor-specific PCI capability, added to the root port
38 Capability layout (defined in include/hw/pci/pci_bridge.h):
40 uint8_t id; Standard PCI capability header field
41 uint8_t next; Standard PCI capability header field
42 uint8_t len; Standard PCI vendor-specific capability header field
44 uint8_t type; Red Hat vendor-specific capability type
62 At the moment this capability is used only in QEMU generic PCIe root port
63 (-device pcie-root-port). Capability construction function takes all reservation
87 - Root ports: 1 QEMU generic root port with the capability mentioned above,
88 2 QEMU generic root ports without this capability;
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| H A D | pcie_sriov.txt | 6 SR/IOV (Single Root I/O Virtualization) is an optional extended capability
24 capability. All VFs have the same BARs and BAR sizes.
34 you would need to add a PCI Express capability in the normal PCI
35 capability list. You might also want to add an ARI (Alternative
36 Routing-ID Interpretation) capability to indicate that your device
54 /* Add and initialize the SR/IOV capability */
74 except for the SR/IOV capability. Then you need to set up the VF BARs as
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| /qemu/include/hw/cxl/ |
| H A D | cxl_component.h | 35 * Capability registers are defined at the top of the CXL.cache/mem region and
41 /* CXL r3.1 Section 8.2.4.1: CXL Capability Header Register */
61 * Capability structures contain the actual registers that the CXL component
66 /* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */
107 /* CXL r3.1 Section 8.2.4.18: CXL Security Capability Structure */
112 /* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */
118 /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */
182 * CXL r3.1 Section 8.2.4.21: CXL Extended Security Capability Structure
191 /* CXL r3.1 Section 8.2.4.22: CXL IDE Capability Structure */
197 /* CXL r3.1 Section 8.2.4.23 - CXL Snoop Filter Capability Structure */
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| H A D | cxl_device.h | 21 * capability headers start at offset 0 and are contiguously packed. The headers
50 * ^ | Memory Device Capability Header|
52 * | | Mailbox Capability Header |
54 * | | Device Capability Header |
63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */
287 * Helper macro to initialize capability headers for CXL devices.
289 * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
614 * total_capacity is equivalent to the dynamic capability
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| /qemu/hw/xen/ |
| H A D | xen_pt_config_init.c | 35 /* A return value of 1 means the capability should NOT be exposed to guest. */
40 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE in xen_pt_hide_dev_cap()
48 * PCI Express Capability Structure of the VF of Intel 82599 10GbE in xen_pt_hide_dev_cap()
50 * Register is 0, so the Capability Version is 0 and in xen_pt_hide_dev_cap()
783 * Vital Product Data Capability
786 /* Vital Product Data Capability Structure reg static information table */
814 * Vendor Specific Capability
817 /* Vendor Specific Capability Structure reg static information table */
836 * PCI Express Capability
920 /* PCI Express Capability Structure reg static information table */
[all …]
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| /qemu/linux-headers/linux/ |
| H A D | vfio_zdev.h | 20 * This capability provides a set of descriptive information about the
40 * This capability provides a set of descriptive information about the group of
62 * This capability provides the utility string for the associated device, which
75 * This capability provides the PCI function path string, which is an identifier
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| H A D | vfio_ccw.h | 28 * Note: this is controlled by a capability
40 * Note: this is controlled by a capability
49 * Note: this is controlled by a capability
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| H A D | vfio.h | 30 * capability is subject to change as groups are added or removed.
54 * devices, so this capability is subject to change as groups are added or
74 * For extension of INFO ioctls, VFIO makes use of a capability chain
76 * this capability chain is supported and a field defined in the fixed
77 * structure defines the offset of the first capability in the chain.
80 * INFO buffer, as is the next field within each capability header.
82 * while the version field is specific to the capability id. The
83 * contents following the header are specific to the capability id.
86 __u16 id; /* Identifies capability */
87 __u16 version; /* Version specific to the capability ID */
[all …]
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| /qemu/include/standard-headers/linux/ |
| H A D | pci_regs.h | 56 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
122 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
208 /* Capability lists */
210 #define PCI_CAP_LIST_ID 0 /* Capability ID */
232 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
233 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
270 #define PCI_AGP_RFU 3 /* Rest of capability flags */
313 #define PCI_MSI_RFU 3 /* Rest of capability flags */
323 /* MSI-X registers (in MSI-X capability) */
371 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
[all …]
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| H A D | virtio_pci.h | 117 /* Additional shared memory capability */
122 /* This is the PCI capability header: */
126 uint8_t cap_len; /* Generic PCI field: capability length */
135 /* This is the PCI vendor data capability header: */
139 uint8_t cap_len; /* Generic PCI field: capability length */
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| /qemu/include/system/ |
| H A D | host_iommu_device.h | 85 * @get_cap: check if a host IOMMU device capability is supported.
92 * @cap: capability to check.
94 * @errp: pass an Error out when fails to query capability.
119 * Host IOMMU device capability list.
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| /qemu/include/hw/pci/ |
| H A D | pcie_regs.h | 12 /* express capability */
14 #define PCI_EXP_VER1_SIZEOF 0x14 /* express capability of ver. 1 */
15 #define PCI_EXP_VER2_SIZEOF 0x3c /* express capability of ver. 2 */
181 /* DOE Capability Register Fields */
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| H A D | pci_bridge.h | 165 uint8_t id; /* Standard PCI capability header field */
166 uint8_t next; /* Standard PCI capability header field */
167 uint8_t len; /* Standard PCI vendor-specific capability header field */
168 uint8_t type; /* Red Hat vendor-specific capability type.
185 * capability in PCI configuration space to reserve on firmware init.
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| H A D | pcie.h | 59 /* Offset of express capability in config space */
89 /* PCI express capability helper functions */
126 /* ARI forwarding capability and control */
131 /* PCI express extended capability helper functions */
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| H A D | pcie_sriov.h | 48 * @offset: The offset of the SR-IOV capability.
51 * Initializes a PF with user-created VFs, adding the ARI extended capability to
77 /* SR/IOV capability config write handler */
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| /qemu/tests/qemu-iotests/tests/ |
| H A D | qsd-migrate.out | 14 …et-capabilities", "arguments": {"capabilities": [{"capability": "events", "state": true}, {"capabi…
16 …et-capabilities", "arguments": {"capabilities": [{"capability": "events", "state": true}, {"capabi…
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| H A D | migrate-bitmaps-test | 89 mig_caps = [{'capability': 'events', 'state': True}]
91 mig_caps.append({'capability': 'dirty-bitmaps', 'state': True})
147 mig_caps = [{'capability': 'events', 'state': True}]
149 mig_caps.append({'capability': 'dirty-bitmaps', 'state': True})
257 caps = [{'capability': 'events', 'state': True}]
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| /qemu/hw/s390x/ |
| H A D | s390-pci-vfio.c | 41 * a big enough buffer to hold the entire capability chain. in s390_pci_update_dma_avail()
56 /* If the capability exists, update with the current value */ in s390_pci_update_dma_avail()
116 /* If capability not provided, just leave the defaults in place */ in s390_pci_read_base()
194 * If capability not provided or the underlying hostdev is simulated, just in s390_pci_read_group()
271 /* If capability not provided, just leave the defaults in place */ in s390_pci_read_util()
298 /* If capability not provided, just leave the defaults in place */ in s390_pci_read_pfip()
325 * if a fh could not be obtained (ioctl failed or capability version does
348 * found in the capability chain; defaults will remain for any CLP features not
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| /qemu/tests/migration-stress/guestperf/ |
| H A D | engine.py | 138 { "capability": "auto-converge",
147 { "capability": "postcopy-ram",
152 { "capability": "postcopy-ram",
165 { "capability": "compress",
172 { "capability": "compress",
181 { "capability": "xbzrle",
186 { "capability": "xbzrle",
204 { "capability": "multifd",
211 { "capability": "multifd",
230 { "capability": "dirty-limit",
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| /qemu/backends/tpm/ |
| H A D | tpm_util.c | 230 uint32_t capability; in tpm_util_get_buffer_size() member
239 .capability = cpu_to_be32(TPM_CAP_PROPERTY), in tpm_util_get_buffer_size()
274 uint32_t capability; in tpm_util_get_buffer_size() member
283 .capability = cpu_to_be32(TPM2_CAP_TPM_PROPERTIES), in tpm_util_get_buffer_size()
290 uint32_t capability; in tpm_util_get_buffer_size() member
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| /qemu/qapi/ |
| H A D | misc-arm.json | 9 # The struct describes capability for a specific GIC (Generic
34 # capability bits.
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| /qemu/docs/devel/migration/ |
| H A D | vfio.rst | 20 enabling "switchover-ack" migration capability.
23 before stopping the source VM. Enabling this migration capability will
68 "switchover-ack" migration capability when this capability is enabled.
125 Discovering device capability, starting and stopping dirty tracking, and
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| /qemu/hw/pci/ |
| H A D | pcie.c | 67 * pci express capability helper functions
76 /* capability register in pcie_cap_v1_fill()
82 /* device capability register in pcie_cap_v1_fill()
249 /* read-only to behave like a 'NULL' Extended Capability Header */ in pcie_cap_init()
667 PCI express capability slot registers */
1000 * pci express extended capability list management functions
1016 /* no extended capability */ in pcie_find_capability_list()
1055 * overlap with other capability or other registers.
1073 * internally to find the last capability in the linked list. in pcie_add_capability()
1081 /* Make capability read-only by default */ in pcie_add_capability()
[all …]
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| /qemu/include/hw/display/ |
| H A D | dpcd.h | 68 /* Receiver port capability. */
74 /* Down stream port capability. */
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| /qemu/docs/specs/ |
| H A D | ivshmem-spec.rst | 41 - If you additionally need the capability for peers to interrupt each
84 MSI-X capability: INTx is asserted when the bit-wise AND of Status and
85 Mask is non-zero and the device has no MSI-X capability. Interrupt
118 If the peer is a revision 0 device without MSI-X capability, its
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