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/src/sys/contrib/device-tree/Bindings/net/can/
H A Drenesas,rcar-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
15 - items:
16 - enum:
17 - renesas,r8a774a1-canfd # RZ/G2M
18 - renesas,r8a774b1-canfd # RZ/G2N
[all …]
H A Drockchip,rk3568v2-canfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/rockchip,rk3568v2-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Rockchip CAN-FD controller
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - const: rockchip,rk3568v2-canfd
20 - items:
21 - const: rockchip,rk3568v3-canfd
[all …]
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Xilinx CAN and CANFD controller
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
29 maxItems: 2
[all …]
H A Drenesas,rcar-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN Controller
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,can-r8a7778 # R-Car M1-A
18 - renesas,can-r8a7779 # R-Car H1
[all …]
H A Dctu,ctucanfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CTU CAN FD Open-source IP Core
10 Open-source CAN FD IP core developed at the Czech Technical University in Prague
14 [2] datasheet : https://canbus.pages.fel.cvut.cz/ctucanfd_ip_core/doc/Datasheet.pdf
18 [3] project : https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top
21 …tps://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-ca…
24 - Pavel Pisa <pisa@cmp.felk.cvut.cz>
25 - Ondrej Ille <ondrej.ille@gmail.com>
[all …]
/src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3568-mecsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/pwm/pwm.h>
20 stdout-path = "serial2:1500000n8";
23 tas2562-sound {
24 compatible = "simple-audio-card";
25 simple-audio-card,format = "i2s";
[all …]
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
/src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a09g047e57-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
27 #include <dt-bindings/gpio/gpio.h>
28 #include <dt-bindings/input/input.h>
29 #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
31 #include "rzg3e-smarc-som.dtsi"
32 #include "renesas-smarc2.dtsi"
35 model = "Renesas SMARC EVK version 2 based on r9a09g047e57";
36 compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
39 vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
[all …]
H A Drzg2lc-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
20 osc1: cec-clock {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
26 hdmi-out {
[all …]
H A Dwhite-hawk-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 #include "white-hawk-csi-dsi.dtsi"
10 #include "white-hawk-ethernet.dtsi"
13 can_transceiver0: can-phy0 {
15 #phy-cells = <0>;
16 enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
17 max-bitrate = <5000000>;
22 clock-frequency = <40000000>;
25 &canfd {
26 pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>;
[all …]
H A Drenesas-smarc2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
13 * 0 - SMARC SDIO signal is connected to uSD1
14 * 1 - SMARC SDIO signal is connected to M.2 Key E connector
20 * 0 - Connect to GPIO8 PMOD (default)
21 * 1 - Connect to CAN0 transceiver STB pin
24 * 0 - Connect to GPIO9 PMOD (default)
25 * 1 - Connect to CAN1 transceiver STB pin
32 model = "Renesas RZ SMARC Carrier-II Board";
33 compatible = "renesas,smarc2-evk";
[all …]
H A Drzg2ul-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
8 #include <dt-bindings/gpio/gpio.h>
9 #include "rzg2ul-smarc-pinfunction.dtsi"
10 #include "rz-smarc-common.dtsi"
13 &canfd {
14 /delete-property/ pinctrl-0;
15 /delete-property/ pinctrl-names;
21 sound-dai = <&ssi1>;
25 clock-frequency = <400000>;
[all …]
H A Debisu.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Ebisu/Ebisu-4D board
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
33 stdout-path = "serial0:115200n8";
36 audio_clkout: audio-clkout {
39 * but needed to avoid cs2000/rcar_sound probe dead-lock
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <11289600>;
[all …]
H A Dr9a07g043.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/r9a07g043-cpg.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 audio_clk1: audio1-clk {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
19 clock-frequency = <0>;
22 audio_clk2: audio2-clk {
23 compatible = "fixed-clock";
[all …]
H A Drz-smarc-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * SSI-WM8978
32 stdout-path = "serial0:115200n8";
36 compatible = "simple-audio-card";
37 simple-audio-card,format = "i2s";
38 simple-audio-card,bitclock-master = <&cpu_dai>;
39 simple-audio-card,frame-master = <&cpu_dai>;
40 simple-audio-card,mclk-fs = <256>;
[all …]
H A Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
[all …]
H A Dr9a07g054.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr9a07g044.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
20 clock-frequency = <0>;
23 audio_clk2: audio2-clk {
[all …]
H A Dr8a77980.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
21 compatible = "fixed-clock";
[all …]
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
H A Dr8a77970-eagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Eagle board with R-Car V3M
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
29 stdout-path = "serial0:115200n8";
32 d1p8: regulator-fixed {
33 compatible = "regulator-fixed";
34 regulator-name = "fixed-1.8V";
35 regulator-min-microvolt = <1800000>;
[all …]
H A Dcondor-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Condor board with R-Car V3H
8 #include <dt-bindings/gpio/gpio.h>
23 stdout-path = "serial0:115200n8";
27 d1_8v: regulator-2 {
28 compatible = "regulator-fixed";
29 regulator-name = "D1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-boot-on;
[all …]
H A Dr8a779h0.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
8 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
17 /* External Audio clock - to be overridden by boards that provide it */
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-mx8menlo.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Copyright 2021-2022 Marek Vasut <marex@denx.de>
6 /dts-v1/;
8 #include "imx8mm-verdin.dtsi"
13 "toradex,verdin-imx8mm-nonwifi",
14 "toradex,verdin-imx8mm",
17 /delete-node/ gpio-keys;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_led>;
[all …]
/src/sys/contrib/device-tree/src/arm64/xilinx/
H A Dversal-net.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 compatible = "xlnx,versal-net";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 interrupt-parent = <&gic>;
21 u-boot {
22 compatible = "u-boot,config";
23 bootscr-address = /bits/ 64 <0x20000000>;
[all …]

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