| /linux-5.10/Documentation/block/ |
| D | writeback_cache_control.rst | 9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
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| /linux-5.10/arch/sparc/include/asm/ |
| D | viking.h | 27 * and never caches them internally (or so states the docs). Therefore
38 * on chip split I/D caches of the GNU/Viking.
45 * caches will snoop regardless of whether they are enabled, this
46 * takes care of the case where the I or D or both caches are turned
58 * caches, they may be cached by the GNU/MXCC if present and enabled.
72 * caches during that cycle. If disabled, all stores operations
78 * These bits enable the on-cpu GNU/Viking split I/D caches. Note,
79 * as mentioned above, these caches will snoop the bus in GNU/MBUS
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| /linux-5.10/arch/c6x/platforms/ |
| D | cache.c | 14 * Internal Memory Control Registers for caches
107 * L1 & L2 caches generic functions
208 * L1 caches management
212 * Disable L1 caches
226 * Enable L1 caches
282 * L2 caches management
422 * L1 and L2 caches configuration
439 /* Set L2 caches on the the whole L2 SRAM memory */ in c6x_cache_init()
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| /linux-5.10/arch/openrisc/ |
| D | Kconfig | 84 bool "Have write through data caches"
87 Select this if your implementation features write through data caches.
89 caches at relevant times. Most OpenRISC implementations support write-
90 through data caches.
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| /linux-5.10/include/linux/ |
| D | kvm_types.h | 65 * Memory caches are used to preallocate memory ahead of various MMU flows,
68 * holding MMU locks. Note, these caches act more like prefetch buffers than
69 * classical caches, i.e. objects are not returned to the cache on being freed.
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| /linux-5.10/Documentation/filesystems/nfs/ |
| D | rpc-cache.rst | 9 Caches subtitle
13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
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| /linux-5.10/arch/arm64/kernel/ |
| D | cacheinfo.c | 57 /* Separate instruction and data caches */ in __init_cache_level()
68 * some external caches not specified in CLIDR_EL1 in __init_cache_level()
70 * only unified external caches are considered here in __init_cache_level()
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| /linux-5.10/arch/mips/kernel/ |
| D | bmips_5xxx_init.S | 300 * Description: Enable I and D caches, initialize I and D-caches, also set
323 * Description: Enable I and D caches, and initialize I and D-caches
344 /* Enable Caches before Clearing. If the caches are disabled
715 * Description: Enable I and D caches, and initialize I and D-caches
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| /linux-5.10/arch/mips/include/asm/ |
| D | io.h | 495 * The caches on some architectures aren't dma-coherent and have need to
499 * - dma_cache_wback_inv(start, size) makes caches and coherent by
500 * writing the content of the caches back to memory, if necessary.
501 * The function also invalidates the affected part of the caches as
503 * - dma_cache_wback(start, size) makes caches and coherent by
504 * writing the content of the caches back to memory, if necessary.
505 * The function also invalidates the affected part of the caches as
508 * caches. Dirty lines of the caches may be written back or simply
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| /linux-5.10/tools/cgroup/ |
| D | memcg_slabinfo.py | 184 caches = {}
203 caches[addr] = cache
215 for addr in caches:
217 cache_show(caches[addr], cfg, stats[addr])
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| /linux-5.10/arch/mips/mm/ |
| D | c-r4k.c | 76 * separate caches). in r4k_op_needs_ipi()
499 * These caches are inclusive caches, that is, if something in local_r4k___flush_cache_all()
501 * in one of the primary caches. in local_r4k___flush_cache_all()
580 * whole caches when vma is executable.
620 * only flush the primary caches but R1x000 behave sane ... in local_r4k_flush_cache_mm()
622 * caches, so we can bail out early. in local_r4k_flush_cache_mm()
881 * Either no secondary cache or the available caches don't have the in r4k_dma_cache_wback_inv()
882 * subset property so we have to flush the primary caches in r4k_dma_cache_wback_inv()
985 * Aliases only affect the primary caches so don't bother with in local_r4k_flush_kernel_vmap_range_index()
986 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index()
[all …]
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| /linux-5.10/arch/powerpc/platforms/52xx/ |
| D | lite5200_sleep.S | 72 /* flush caches [destroys r3, r4] */
93 /* disable I and D caches */
226 /* invalidate caches */
229 mtspr SPRN_HID0, r5 /* invalidate caches */
234 /* enable caches */
236 mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
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| /linux-5.10/arch/powerpc/boot/ |
| D | gamecube-head.S | 14 * - if the data and instruction caches are enabled or not
17 * We enable the caches if not already enabled, enable the MMU with an
75 /* enable and invalidate the caches if not already enabled */
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| D | wii-head.S | 14 * - if the data and instruction caches are enabled or not
18 * We enable the high BATs, enable the caches if not already enabled,
99 /* enable and invalidate the caches if not already enabled */
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| /linux-5.10/drivers/gpu/drm/i915/ |
| D | i915_globals.c | 120 * Defer shrinking the global slab caches (and other work) until in i915_globals_park()
123 * by us shrinking the caches the same time as they are trying to in i915_globals_park()
126 * to be longer until we need the caches again. in i915_globals_park()
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| /linux-5.10/arch/arm/mm/ |
| D | proc-sa1100.S | 50 * - Clean and turn off caches.
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
120 * Clean the specified entry of any caches such that the MMU
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| D | proc-arm926.S | 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
184 * Harvard caches, you need to implement this function.
197 * Harvard caches, you need to implement this function.
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mov r0, #4 @ disable write-back on caches explicitly
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| D | proc-sa110.S | 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
110 * Clean the specified entry of any caches such that the MMU
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
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| D | proc-mohawk.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
155 * Harvard caches, you need to implement this function.
168 * Harvard caches, you need to implement this function.
359 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
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| D | proc-arm920.S | 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
173 * Harvard caches, you need to implement this function.
186 * Harvard caches, you need to implement this function.
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| /linux-5.10/arch/arm/boot/compressed/ |
| D | head-xscale.S | 28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
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| D | head-sa1100.S | 42 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
44 @ disabling MMU and caches
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| /linux-5.10/Documentation/core-api/ |
| D | cachetlb.rst | 121 us to properly handle systems whose caches are strict and require
129 indexed caches which must be flushed when virtual-->physical
131 indexed physically tagged caches of IA32 processors have no need to
132 implement these interfaces since the caches are fully synchronized
140 the caches. That is, after running, there will be no cache
149 the caches. That is, after running, there will be no cache
156 optimizations for VIPT caches.
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| /linux-5.10/arch/mips/fw/arc/ |
| D | promlib.c | 7 * Compatibility with board caches, Ulf Carlsson
30 * IP22 boardcache is not compatible with board caches. Thus we disable it
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| /linux-5.10/arch/sh/mm/ |
| D | cache-sh2a.c | 47 * Write back the dirty D-caches, but not invalidate them.
89 * Write back the dirty D-caches and invalidate them.
119 * Invalidate the D-caches, but no write back please
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