Searched full:cacheability (Results 1 – 25 of 29) sorted by relevance
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| /linux-6.8/arch/x86/include/asm/ |
| D | agp.h | 12 * mappings with different cacheability attributes for the same
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| D | set_memory.h | 15 * Cacheability : UnCached, WriteCombining, WriteThrough, WriteBack
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| /linux-6.8/Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic-v3.yaml | 112 and cacheability attributes but are connected to a non-coherent
205 cacheability attributes but is connected to a non-coherent
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| /linux-6.8/drivers/iommu/ |
| D | msm_iommu.h | 16 /* Cacheability attributes of MSM IOMMU mappings */
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| /linux-6.8/arch/sparc/include/asm/ |
| D | swift.h | 21 #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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| /linux-6.8/arch/powerpc/kernel/ |
| D | cpu_setup_ppc970.S | 41 li r3,0x1200 /* enable i-fetch cacheability */
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| /linux-6.8/drivers/gpu/drm/imagination/ |
| D | pvr_fw_mips.c | 225 /* MIPS cacheability is determined by page table. */ in pvr_mips_get_fw_addr_with_offset()
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| D | pvr_fw_meta.c | 510 /* META cacheability is determined by address. */ in pvr_meta_get_fw_addr_with_offset()
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| D | pvr_rogue_meta.h | 277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
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| /linux-6.8/include/linux/ |
| D | io-pgtable.h | 86 * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
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| /linux-6.8/arch/powerpc/include/asm/ |
| D | reg_booke.h | 180 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
181 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
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| /linux-6.8/arch/arm/include/asm/ |
| D | io.h | 340 * Function Memory type Cacheability Cache hint
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| /linux-6.8/drivers/gpu/drm/i915/gt/ |
| D | intel_gtt.h | 107 * Cacheability Control is a 4-bit value. The low three bits are stored in bits
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| D | intel_gtt.c | 605 * The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
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| D | intel_mocs.c | 146 * Thus it is expected to allow LLC cacheability to enable coherent
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| /linux-6.8/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3.h | 94 /* CR1 cacheability fields don't quite follow the usual TCR-style encoding */
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| /linux-6.8/Documentation/driver-api/ |
| D | device-io.rst | 440 | API | Memory region type and cacheability |
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| /linux-6.8/arch/riscv/ |
| D | Kconfig | 512 that indicate the cacheability, idempotency, and ordering
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| /linux-6.8/drivers/irqchip/ |
| D | irq-gic-v3-its.c | 3145 * remove the cacheability attributes as in its_cpu_init_lpis()
3171 * cacheability attributes as well. in its_cpu_init_lpis()
5163 * remove the cacheability attributes as in its_probe_one()
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| /linux-6.8/include/uapi/drm/ |
| D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /linux-6.8/tools/include/uapi/drm/ |
| D | i915_drm.h | 134 * MOCS indexes used for GPU surfaces, defining the cacheability of the
144 * Cacheability and coherency controlled by the kernel automatically
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| /linux-6.8/arch/mips/ |
| D | Kconfig | 1044 # MIPS allows mixing "slightly different" Cacheability and Coherency
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| /linux-6.8/arch/arm64/kvm/ |
| D | mmu.c | 304 * we then fully enforce cacheability of RAM, no matter what the guest
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| /linux-6.8/arch/sparc/mm/ |
| D | init_64.c | 2337 * set on M7 processor. Compute the value of cacheability in paging_init()
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| /linux-6.8/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.c | 2273 * Program cacheability overrides to not allocate cache in a6xx_llc_activate()
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