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/linux-6.8/arch/arm/include/asm/hardware/
D	cp14.h	`45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0) 46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0) 47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0) 48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0) 49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0) 50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0) 51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0) 52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0) 53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2) 54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2) [all …]`
/linux-6.8/tools/testing/selftests/hid/tests/
D	test_multitouch.py	492 …c0 c0 05 0d 09 06 15 00 26 ff 00 a1 01 85 02 75 08 95 3f 09 00 82 02 01 95 3f 09 00 92 02 01 c0 05… 1112 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 01 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1123 …c0 a1 02 15 00 26 ff 00 09 01 95 39 75 08 81 03 c0 c0 05 0d 09 0e a1 01 85 11 09 23 a1 02 09 52 09… 1134 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1171 …c0 09 22 a1 02 05 0d 35 00 45 00 55 00 65 00 09 42 25 01 75 01 81 02 09 32 81 02 09 47 81 02 75 05… 1181 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1190 …6 0a 26 ff 0f 09 30 81 02 46 b2 05 26 ff 0f 09 31 81 02 05 0d 75 08 85 02 09 55 25 10 b1 02 c0 c0", 1199 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1208 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81 02 95 05 81 03 09 51 75 08… 1217 …c0 05 01 09 02 a1 01 09 01 a1 00 85 01 05 09 19 01 29 03 15 00 25 01 95 03 75 01 81 02 95 01 75 05… [all …]
D	test_tablet.py	995 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1003 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1011 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1019 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1027 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1035 …c0 c0 05 01 09 01 a1 01 85 01 09 01 a1 00 05 09 19 01 29 02 15 00 25 01 95 02 75 01 81 02 95 01 75… 1043 …c0 c0 05 0d 09 04 a1 01 85 30 09 22 a1 02 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 09 47 81… 1051 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1060 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… 1069 …c0 a1 02 05 0d 09 42 15 00 25 01 75 01 95 01 81 02 09 32 81 02 95 06 81 03 75 08 09 51 95 01 81 02… [all …]
/linux-6.8/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
D	g98.fuc0s	`514 cxsin $c0 515 cxsout $c0 525 cxsin $c0 526 cenc $c0 $c0 527 cxsout $c0 533 cxsin $c0 534 cdec $c0 $c0 535 cxsout $c0 540 cxsin $c0 541 cxor $c6 $c0 [all …]`
/linux-6.8/arch/arm/mm/
D	proc-v7.S	`34 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 37 mcr p15, 0, r0, c1, c0, 0 @ disable caches 57 mrc p15, 0, r2, c1, c0, 0 @ ctrl register 60 mcr p15, 0, r2, c1, c0, 0 @ disable MMU 136 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 137 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 140 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 144 mrc p15, 0, r7, c2, c0, 1 @ TTB 1 146 mrc p15, 0, r11, c2, c0, 2 @ TTB control register 148 mrc p15, 0, r8, c1, c0, 0 @ Control register [all …]`
D	proc-v6.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 59 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 61 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 78 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 108 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 113 mcr p15, 0, r1, c13, c0, 1 @ set context ID 141 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 143 mrc p15, 0, r5, c3, c0, 0 @ Domain ID [all …]`
D	proc-sa1100.S	`42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 175 mrc p15, 0, r4, c3, c0, 0 @ domain ID 176 mrc p15, 0, r5, c13, c0, 0 @ PID 177 mrc p15, 0, r6, c1, c0, 0 @ control reg [all …]`
D	proc-arm740.S	`37 mrc p15, 0, r0, c1, c0, 0 40 mcr p15, 0, r0, c1, c0, 0 @ disable caches 51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register 54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 71 mcr p15, 0, r0, c6, c0 @ set area 0, default 97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable 103 mcr p15, 0, r0, c3, c0 107 mcr p15, 0, r0, c5, c0 @ all read/write access [all …]`
D	proc-xsc3.S	`56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches 109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 137 mcr p14, 0, r0, c7, c0, 0 @ go to idle 366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 416 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 418 mrc p15, 0, r6, c13, c0, 0 @ PID [all …]`
D	proc-mohawk.S	`41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register 68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 321 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 345 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 347 mrc p15, 0, r6, c13, c0, 0 @ PID 348 mrc p15, 0, r7, c3, c0, 0 @ domain ID 349 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg [all …]`
D	cache-v7.S	43 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR 45 mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR 68 mrc p15, 1, r0, c0, c0, 0 @ re-read cache geometry from CCSIDR 100 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr 106 ALT_SMP(mrc p15, 0, r2, c0, c0, 0) @ read main ID register 128 mrc p15, 1, r0, c0, c0, 1 @ read clidr 143 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 145 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 179 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
/linux-6.8/tools/testing/selftests/cgroup/
D	test_cpuset_prs.sh	`168 " C0-1 . . C2-3 S+ C4-5 . . 0 A2:0-1" 169 " C0-1 . . C2-3 P1 . . . 0 " 170 " C0-1 . . C2-3 P1:S+ C0-1:P1 . . 0 " 171 " C0-1 . . C2-3 P1:S+ C1:P1 . . 0 " 172 " C0-1:S+ . . C2-3 . . . P1 0 " 173 " C0-1:P1 . . C2-3 S+ C1 . . 0 " 174 " C0-1:P1 . . C2-3 S+ C1:P1 . . 0 " 175 " C0-1:P1 . . C2-3 S+ C1:P1 . P1 0 " 176 " C0-1:P1 . . C2-3 C4-5 . . . 0 A1:4-5" 177 " C0-1:P1 . . C2-3 S+:C4-5 . . . 0 A1:4-5" [all …]`
/linux-6.8/arch/arm/include/debug/
D	icedcc.S	`16 mcr p14, 0, \rd, c0, c5, 0 21 mrc p14, 0, \rx, c0, c1, 0 34 mrc p14, 0, \rx, c0, c1, 0 43 mcr p14, 0, \rd, c8, c0, 0 48 mrc p14, 0, \rx, c14, c0, 0 61 mrc p14, 0, \rx, c14, c0, 0 70 mcr p14, 0, \rd, c1, c0, 0 75 mrc p14, 0, \rx, c0, c0, 0 89 mrc p14, 0, \rx, c0, c0, 0`
/linux-6.8/arch/s390/crypto/
D	chacha-s390.S	`442 #define C0 %v2 macro 514 VLR C0,K2 545 VAF C0,C0,D0 551 VX B0,B0,C0 583 VAF C0,C0,D0 589 VX B0,B0,C0 602 VSLDB C0,C0,C0,8 640 VAF C0,C0,D0 646 VX B0,B0,C0 678 VAF C0,C0,D0 [all …]`
/linux-6.8/drivers/gpu/drm/tidss/
D	tidss_scale_coefs.c	19 .c0 = { 192, 192, 192, 190, 188, 186, 184, 182, 180, }, 25 .c0 = { 200, 202, 204, 202, 200, 196, 192, 188, 184, }, 31 .c0 = { 216, 216, 216, 214, 212, 208, 204, 198, 192, }, 37 .c0 = { 232, 232, 232, 226, 220, 218, 216, 208, 200, }, 43 .c0 = { 264, 262, 260, 254, 248, 242, 236, 226, 216, }, 49 .c0 = { 288, 286, 284, 280, 276, 266, 256, 244, 232, }, 55 .c0 = { 312, 308, 304, 298, 292, 282, 272, 258, 244, }, 61 .c0 = { 336, 332, 328, 320, 312, 300, 288, 272, 256, }, 67 .c0 = { 368, 364, 360, 350, 340, 326, 312, 292, 272, }, 73 .c0 = { 400, 398, 396, 384, 372, 354, 336, 312, 288, }, [all …]
/linux-6.8/arch/arm/kernel/
D	hyp-stub.S	`116 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 126 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 133 mrc p15, 0, r7, c1, c0, 0 @ SCTLR 137 mcr p15, 0, r7, c1, c0, 0 @ SCTLR 139 mrc p15, 0, r7, c0, c0, 0 @ MIDR 140 mcr p15, 4, r7, c0, c0, 0 @ VPIDR 142 mrc p15, 0, r7, c0, c0, 5 @ MPIDR 143 mcr p15, 4, r7, c0, c0, 5 @ VMPIDR 147 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 166 mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 [all …]`
/linux-6.8/arch/arm/boot/compressed/
D	head.S	`38 mcr p14, 0, \ch, c0, c5, 0 44 mcr p14, 0, \ch, c8, c0, 0 50 mcr p14, 0, \ch, c1, c0, 0 141 mrc p15, 0, \reg, c1, c0, 0 @ read SCTLR 145 mcr p15, 0, \reg, c1, c0, 0 @ write SCTLR 696 mrc p15, 0, \tmp, c0, c0, 1 @ read ctr 735 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 736 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 737 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 740 mcr p15, 0, r0, c5, c0, 1 @ I-access permission [all …]`
/linux-6.8/arch/arm/mach-sunxi/
D	headsmp.S	`25 mrc p15, 0, r1, c0, c0, 0 37 mrc p15, 1, r1, c15, c0, 4 39 mcr p15, 1, r1, c15, c0, 4 42 mrc p15, 1, r1, c15, c0, 0 47 mcr p15, 1, r1, c15, c0, 0 50 mrc p15, 1, r1, c9, c0, 2 53 mcr p15, 1, r1, c9, c0, 2`
/linux-6.8/arch/arm/mach-omap2/
D	sleep44xx.S	`88 mrc p15, 0, r0, c1, c0, 0 90 mcr p15, 0, r0, c1, c0, 0 108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR 128 mrcne p15, 0, r0, c1, c0, 1 130 mcrne p15, 0, r0, c1, c0, 1 146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR 189 mrc p15, 0, r0, c1, c0, 0 192 mcreq p15, 0, r0, c1, c0, 0 201 mrc p15, 0, r0, c1, c0, 1 [all …]`
D	omap-headsmp.S	`46 mrc p15, 0, r4, c0, c0, 5 64 mrc p15, 0, r4, c0, c0, 5 86 mrc p15, 0, r4, c0, c0, 5 103 mrc p15, 0, r4, c0, c0, 5`
/linux-6.8/arch/arm/mach-spear/
D	hotplug.c	`28 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 30 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_enter_lowpower() 31 " mrc p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 33 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_enter_lowpower() 43 asm volatile("mrc p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 45 " mcr p15, 0, %0, c1, c0, 0\n" in cpu_leave_lowpower() 46 " mrc p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 1\n" in cpu_leave_lowpower()`
/linux-6.8/tools/testing/selftests/net/forwarding/
D	bridge_igmp.sh	17 MZPKT_IS_INC="22:00:9d:de:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:03" 19 MZPKT_IS_INC2="22:00:9d:c3:00:00:00:01:01:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 21 MZPKT_IS_INC3="22:00:5f:b4:00:00:00:01:01:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 23 MZPKT_ALLOW="22:00:99:c3:00:00:00:01:05:00:00:03:ef:0a:0a:0a:c0:00:02:0a:c0:00:02:0b:c0:00:02:0c" 25 MZPKT_ALLOW2="22:00:5b:b4:00:00:00:01:05:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 27 …_IS_EXC="22:00:da:b6:00:00:00:01:02:00:00:04:ef:0a:0a:0a:c0:00:02:01:c0:00:02:02:c0:00:02:14:c0:00… 29 MZPKT_IS_EXC2="22:00:5e:b4:00:00:00:01:02:00:00:02:ef:0a:0a:0a:c0:00:02:14:c0:00:02:1e" 31 MZPKT_TO_EXC="22:00:9a:b1:00:00:00:01:04:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e" 33 MZPKT_BLOCK="22:00:98:b1:00:00:00:01:06:00:00:03:ef:0a:0a:0a:c0:00:02:01:c0:00:02:14:c0:00:02:1e"
/linux-6.8/arch/arm/mach-versatile/
D	hotplug.c	30 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 32 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_enter_lowpower() 33 " mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 35 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_enter_lowpower() 46 "mrc p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 0\n" in versatile_immitation_leave_lowpower() 49 " mrc p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower() 51 " mcr p15, 0, %0, c1, c0, 1\n" in versatile_immitation_leave_lowpower()
/linux-6.8/Documentation/admin-guide/hw-vuln/
D	cross-thread-rsb.rst	9 transitions out of C0 state, the other sibling thread could use return target 10 predictions from the sibling thread that transitioned out of C0. 15 transitioning out of C0. This could result in a guest-controlled return target 41 requests to transition out of the C0 state. This can be communicated with the 42 HLT instruction or with an MWAIT instruction that requests non-C0. 43 When the thread re-enters the C0 state, the processor transitions back 44 to 2T mode, assuming the other thread is also still in C0 state. 62 instructions with targeted return locations and then transitioning out of C0 86 attempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS
/linux-6.8/arch/arm/mach-tegra/
D	sleep.h	`70 mrc p15, 0, \rd, c0, c0, 5 82 mrc p15, 0, \tmp1, c0, c0, 0 90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR 92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR 96 mrceq p15, 0, \tmp1, c0, c0, 5`

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