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/qemu/tests/qtest/libqos/
H A Dpci-spapr.c25 static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr) in qpci_spapr_pio_readb() argument
27 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); in qpci_spapr_pio_readb()
28 return qtest_readb(bus->qts, s->pio_cpu_base + addr); in qpci_spapr_pio_readb()
31 static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val) in qpci_spapr_pio_writeb() argument
33 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); in qpci_spapr_pio_writeb()
34 qtest_writeb(bus->qts, s->pio_cpu_base + addr, val); in qpci_spapr_pio_writeb()
37 static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr) in qpci_spapr_pio_readw() argument
39 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); in qpci_spapr_pio_readw()
40 return bswap16(qtest_readw(bus->qts, s->pio_cpu_base + addr)); in qpci_spapr_pio_readw()
43 static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val) in qpci_spapr_pio_writew() argument
[all …]
H A Dgeneric-pcihost.c27 if (!g_strcmp0(device, "pci-bus-generic")) { in generic_pcihost_get_device()
42 static uint8_t qpci_generic_pio_readb(QPCIBus *bus, uint32_t addr) in qpci_generic_pio_readb() argument
44 QGenericPCIBus *s = container_of(bus, QGenericPCIBus, bus); in qpci_generic_pio_readb()
46 return qtest_readb(bus->qts, s->gpex_pio_base + addr); in qpci_generic_pio_readb()
49 static void qpci_generic_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val) in qpci_generic_pio_writeb() argument
51 QGenericPCIBus *s = container_of(bus, QGenericPCIBus, bus); in qpci_generic_pio_writeb()
53 qtest_writeb(bus->qts, s->gpex_pio_base + addr, val); in qpci_generic_pio_writeb()
56 static uint16_t qpci_generic_pio_readw(QPCIBus *bus, uint32_t addr) in qpci_generic_pio_readw() argument
58 QGenericPCIBus *s = container_of(bus, QGenericPCIBus, bus); in qpci_generic_pio_readw()
60 return qtest_readw(bus->qts, s->gpex_pio_base + addr); in qpci_generic_pio_readw()
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H A Dpci-pc.c24 static uint8_t qpci_pc_pio_readb(QPCIBus *bus, uint32_t addr) in qpci_pc_pio_readb() argument
26 return qtest_inb(bus->qts, addr); in qpci_pc_pio_readb()
29 static void qpci_pc_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val) in qpci_pc_pio_writeb() argument
31 qtest_outb(bus->qts, addr, val); in qpci_pc_pio_writeb()
34 static uint16_t qpci_pc_pio_readw(QPCIBus *bus, uint32_t addr) in qpci_pc_pio_readw() argument
36 return qtest_inw(bus->qts, addr); in qpci_pc_pio_readw()
39 static void qpci_pc_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val) in qpci_pc_pio_writew() argument
41 qtest_outw(bus->qts, addr, val); in qpci_pc_pio_writew()
44 static uint32_t qpci_pc_pio_readl(QPCIBus *bus, uint32_t addr) in qpci_pc_pio_readl() argument
46 return qtest_inl(bus->qts, addr); in qpci_pc_pio_readl()
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H A Dpci.c22 void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id, in qpci_device_foreach() argument
34 dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn)); in qpci_device_foreach()
58 return dev->bus->has_buggy_msi; in qpci_has_buggy_msi()
70 static void qpci_device_set(QPCIDevice *dev, QPCIBus *bus, int devfn) in qpci_device_set() argument
74 dev->bus = bus; in qpci_device_set()
78 QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn) in qpci_device_find() argument
83 qpci_device_set(dev, bus, devfn); in qpci_device_find()
93 void qpci_device_init(QPCIDevice *dev, QPCIBus *bus, QPCIAddress *addr) in qpci_device_init() argument
97 qpci_device_set(dev, bus, addr->devfn); in qpci_device_init()
134 static void qpci_secondary_buses_rec(QPCIBus *qbus, int bus, int *pci_bus) in qpci_secondary_buses_rec() argument
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H A Dpci.h27 uint8_t (*pio_readb)(QPCIBus *bus, uint32_t addr);
28 uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr);
29 uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr);
30 uint64_t (*pio_readq)(QPCIBus *bus, uint32_t addr);
32 void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value);
33 void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value);
34 void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value);
35 void (*pio_writeq)(QPCIBus *bus, uint32_t addr, uint64_t value);
37 void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len);
38 void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, size_t len);
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/qemu/hw/core/
H A Dbus.c26 void qbus_set_hotplug_handler(BusState *bus, Object *handler) in qbus_set_hotplug_handler() argument
28 object_property_set_link(OBJECT(bus), QDEV_HOTPLUG_HANDLER_PROPERTY, in qbus_set_hotplug_handler()
32 void qbus_set_bus_hotplug_handler(BusState *bus) in qbus_set_bus_hotplug_handler() argument
34 qbus_set_hotplug_handler(bus, OBJECT(bus)); in qbus_set_bus_hotplug_handler()
37 int qbus_walk_children(BusState *bus, in qbus_walk_children() argument
46 err = pre_busfn(bus, opaque); in qbus_walk_children()
53 QTAILQ_FOREACH_RCU(kid, &bus->children, sibling) { in qbus_walk_children()
64 err = post_busfn(bus, opaque); in qbus_walk_children()
73 void bus_cold_reset(BusState *bus) in bus_cold_reset() argument
75 resettable_reset(OBJECT(bus), RESET_TYPE_COLD); in bus_cold_reset()
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/qemu/hw/i2c/
H A Daspeed_i2c.c38 static inline void aspeed_i2c_bus_raise_interrupt(AspeedI2CBus *bus) in aspeed_i2c_bus_raise_interrupt() argument
40 AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); in aspeed_i2c_bus_raise_interrupt()
41 uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); in aspeed_i2c_bus_raise_interrupt()
42 uint32_t intr_ctrl_reg = aspeed_i2c_bus_intr_ctrl_offset(bus); in aspeed_i2c_bus_raise_interrupt()
43 uint32_t intr_ctrl_mask = bus->regs[intr_ctrl_reg] | in aspeed_i2c_bus_raise_interrupt()
49 aspeed_i2c_bus_pkt_mode_en(bus) && in aspeed_i2c_bus_raise_interrupt()
50 ARRAY_FIELD_EX32(bus->regs, I2CM_INTR_STS, PKT_CMD_DONE) ? in aspeed_i2c_bus_raise_interrupt()
52 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_NAK) ? in aspeed_i2c_bus_raise_interrupt()
54 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, TX_ACK) ? in aspeed_i2c_bus_raise_interrupt()
56 SHARED_ARRAY_FIELD_EX32(bus->regs, reg_intr_sts, RX_DONE) ? in aspeed_i2c_bus_raise_interrupt()
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H A Dsmbus_master.c19 int smbus_quick_command(I2CBus *bus, uint8_t addr, int read) in smbus_quick_command() argument
21 if (i2c_start_transfer(bus, addr, read)) { in smbus_quick_command()
24 i2c_end_transfer(bus); in smbus_quick_command()
28 int smbus_receive_byte(I2CBus *bus, uint8_t addr) in smbus_receive_byte() argument
32 if (i2c_start_recv(bus, addr)) { in smbus_receive_byte()
35 data = i2c_recv(bus); in smbus_receive_byte()
36 i2c_nack(bus); in smbus_receive_byte()
37 i2c_end_transfer(bus); in smbus_receive_byte()
41 int smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data) in smbus_send_byte() argument
43 if (i2c_start_send(bus, addr)) { in smbus_send_byte()
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H A Dcore.c2 * QEMU I2C bus interface.
33 I2CBus *bus = opaque; in i2c_bus_pre_save() local
35 bus->saved_address = -1; in i2c_bus_pre_save()
36 if (!QLIST_EMPTY(&bus->current_devs)) { in i2c_bus_pre_save()
37 if (!bus->broadcast) { in i2c_bus_pre_save()
38 bus->saved_address = QLIST_FIRST(&bus->current_devs)->elt->address; in i2c_bus_pre_save()
40 bus->saved_address = I2C_BROADCAST; in i2c_bus_pre_save()
58 /* Create a new I2C bus. */
61 I2CBus *bus; in i2c_init_bus() local
63 bus = I2C_BUS(qbus_new(TYPE_I2C_BUS, parent, name)); in i2c_init_bus()
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/qemu/hw/virtio/
H A Dvirtio-bus.c29 #include "hw/virtio/virtio-bus.h"
46 BusState *qbus = BUS(qdev_get_parent_bus(qdev)); in virtio_bus_device_plugged()
47 VirtioBusState *bus = VIRTIO_BUS(qbus); in virtio_bus_device_plugged() local
48 VirtioBusClass *klass = VIRTIO_BUS_GET_CLASS(bus); in virtio_bus_device_plugged()
102 void virtio_bus_reset(VirtioBusState *bus) in virtio_bus_reset() argument
104 VirtIODevice *vdev = virtio_bus_get_device(bus); in virtio_bus_reset()
106 DPRINTF("%s: reset device.\n", BUS(bus)->name); in virtio_bus_reset()
107 virtio_bus_stop_ioeventfd(bus); in virtio_bus_reset()
117 BusState *qbus = BUS(qdev_get_parent_bus(qdev)); in virtio_bus_device_unplugged()
130 uint16_t virtio_bus_get_vdev_id(VirtioBusState *bus) in virtio_bus_get_vdev_id() argument
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/qemu/include/hw/i2c/
H A Di2c.h42 * Notify the slave of a bus state change. For start event,
66 #define TYPE_I2C_BUS "i2c-bus"
93 /* Set from slave currently mastering the bus. */
98 int i2c_bus_busy(I2CBus *bus);
101 * i2c_start_transfer: start a transfer on an I2C bus.
103 * @bus: #I2CBus to be used
112 int i2c_start_transfer(I2CBus *bus, uint8_t address, bool is_recv);
115 * i2c_start_recv: start a 'receive' transfer on an I2C bus.
117 * @bus: #I2CBus to be used
122 int i2c_start_recv(I2CBus *bus, uint8_t address);
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/qemu/hw/pci/
H A Dpci.c2 * QEMU PCI bus manager
143 OBJECT(pci_dev), "bus master", in pci_init_bus_master()
152 PCIBus *bus = container_of(notifier, PCIBus, machine_done); in pcibus_machine_done() local
155 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { in pcibus_machine_done()
156 if (bus->devices[i]) { in pcibus_machine_done()
157 pci_init_bus_master(bus->devices[i]); in pcibus_machine_done()
164 PCIBus *bus = PCI_BUS(qbus); in pci_bus_realize() local
166 bus->machine_done.notify = pcibus_machine_done; in pci_bus_realize()
167 qemu_add_machine_init_done_notifier(&bus->machine_done); in pci_bus_realize()
169 vmstate_register_any(NULL, &vmstate_pcibus, bus); in pci_bus_realize()
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H A Dpci-qmp-cmds.c31 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
68 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, in qmp_query_pci_bridge() argument
76 info->bus = g_new0(PciBusInfo, 1); in qmp_query_pci_bridge()
77 info->bus->number = dev->config[PCI_PRIMARY_BUS]; in qmp_query_pci_bridge()
78 info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; in qmp_query_pci_bridge()
79 info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; in qmp_query_pci_bridge()
81 range = info->bus->io_range = g_new0(PciMemoryRange, 1); in qmp_query_pci_bridge()
85 range = info->bus->memory_range = g_new0(PciMemoryRange, 1); in qmp_query_pci_bridge()
89 range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); in qmp_query_pci_bridge()
94 PCIBus *child_bus = pci_find_bus_nr(bus, in qmp_query_pci_bridge()
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/qemu/hw/ide/
H A Dpci.c2 * QEMU IDE Emulation: PCI Bus support.
45 IDEBus *bus = opaque; in pci_ide_status_read() local
50 return ide_status_read(bus, addr + 2); in pci_ide_status_read()
56 IDEBus *bus = opaque; in pci_ide_ctrl_write() local
61 ide_ctrl_write(bus, addr + 2, data); in pci_ide_ctrl_write()
72 IDEBus *bus = opaque; in pci_ide_data_read() local
75 return ide_ioport_read(bus, addr); in pci_ide_data_read()
78 return ide_data_readw(bus, addr); in pci_ide_data_read()
80 return ide_data_readl(bus, addr); in pci_ide_data_read()
89 IDEBus *bus = opaque; in pci_ide_data_write() local
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/qemu/hw/misc/
H A Dauxbus.c26 * This is an implementation of the AUX bus for VESA Display Port v1.1a.
52 /* aux-bus implementation (internal not public) */
65 AUXBus *bus; in aux_bus_init() local
68 bus = AUX_BUS(qbus_new(TYPE_AUX_BUS, parent, name)); in aux_bus_init()
69 auxtoi2c = object_new_with_props(TYPE_AUXTOI2C, OBJECT(bus), "i2c", in aux_bus_init()
72 bus->bridge = AUXTOI2C(auxtoi2c); in aux_bus_init()
75 bus->aux_io = g_malloc(sizeof(*bus->aux_io)); in aux_bus_init()
76 memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", 1 * MiB); in aux_bus_init()
77 address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io"); in aux_bus_init()
78 return bus; in aux_bus_init()
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/qemu/hw/acpi/
H A Dpcihp.c54 PCIBus *bus; member
57 static int acpi_pcihp_get_bsel(PCIBus *bus) in acpi_pcihp_get_bsel() argument
60 uint64_t bsel = object_property_get_uint(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, in acpi_pcihp_get_bsel()
79 static void *acpi_set_bsel(PCIBus *bus, void *opaque) in acpi_set_bsel() argument
83 DeviceState *br = bus->qbus.parent; in acpi_set_bsel()
87 if (qbus_is_hotpluggable(BUS(bus))) { in acpi_set_bsel()
92 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, in acpi_set_bsel()
104 PCIBus *bus; in acpi_set_pci_info() local
117 bus = PCI_HOST_BRIDGE(host)->bus; in acpi_set_pci_info()
118 if (bus) { in acpi_set_pci_info()
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/qemu/include/hw/misc/
H A Dauxbus.h57 #define TYPE_AUX_BUS "aux-bus"
88 * aux_bus_init: Initialize an AUX bus.
90 * Returns the new AUX bus created.
92 * @parent The device where this bus is located.
93 * @name The name of the bus.
98 * aux_bus_realize: Realize an AUX bus.
100 * @bus: The AUX bus.
102 void aux_bus_realize(AUXBus *bus);
105 * aux_request: Make a request on the bus.
109 * @bus The bus where the request happen.
[all …]
/qemu/hw/usb/
H A Dbus.c83 void usb_bus_new(USBBus *bus, size_t bus_size, in usb_bus_new() argument
86 qbus_init(bus, bus_size, TYPE_USB_BUS, host, NULL); in usb_bus_new()
87 qbus_set_bus_hotplug_handler(BUS(bus)); in usb_bus_new()
88 bus->ops = ops; in usb_bus_new()
89 bus->busnr = next_usb_bus++; in usb_bus_new()
90 QTAILQ_INIT(&bus->free); in usb_bus_new()
91 QTAILQ_INIT(&bus->used); in usb_bus_new()
92 QTAILQ_INSERT_TAIL(&busses, bus, next); in usb_bus_new()
95 void usb_bus_release(USBBus *bus) in usb_bus_release() argument
99 QTAILQ_REMOVE(&busses, bus, next); in usb_bus_release()
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/qemu/docs/
H A Dpci_expander_bridge.txt10 on bus 0 (pci.0).
12 As opposed to PCI-2-PCI bridge's secondary bus, PXB's bus
13 is a primary bus and can be associated with a NUMA node
26 -device pxb,id=bridge1,bus=pci.0,numa_node=1,bus_nr=4 -netdev user,id=nd -device e1000,bus=bridge1,…
27 -device pxb,id=bridge2,bus=pci.0,numa_node=0,bus_nr=8 -device e1000,bus=bridge2,addr=0x3
28 -device pxb,id=bridge3,bus=pci.0,bus_nr=40 -drive if=none,id=drive0,file=[img] -device virtio-blk-p…
38 Please observe that we specified the bus "pci.0" for the second and third pxb.
39 This is because when no bus is given, another pxb can be selected by QEMU as default bus,
40 however, PXBs can be placed only under the root bus.
46 The host bridge allows to register and query the PXB's PCI root bus in QEMU.
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H A Dqdev-device-use.txt3 === Specifying Bus and Address on Bus ===
5 In qdev, each device has a parent bus. Some devices provide one or
6 more buses for children. You can specify a device's parent bus with
7 -device parameter bus.
9 A device typically has a device address on its parent bus. For buses
10 where this address can be configured, devices provide a bus-specific
13 bus property name value format
19 virtio-serial-bus nr %u
20 ccid-bus slot %u
23 Example: device i440FX-pcihost is on the root bus, and provides a PCI
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/qemu/hw/isa/
H A Disa-bus.c2 * isa bus support for qdev.
58 error_setg(errp, "Can't create a second ISA bus"); in isa_bus_new()
77 void isa_bus_register_input_irqs(ISABus *bus, qemu_irq *irqs_in) in isa_bus_register_input_irqs() argument
79 bus->irqs_in = irqs_in; in isa_bus_register_input_irqs()
82 qemu_irq isa_bus_get_irq(ISABus *bus, unsigned irqnum) in isa_bus_get_irq() argument
85 assert(bus->irqs_in); in isa_bus_get_irq()
86 return bus->irqs_in[irqnum]; in isa_bus_get_irq()
107 void isa_bus_dma(ISABus *bus, IsaDma *dma8, IsaDma *dma16) in isa_bus_dma() argument
109 assert(bus && dma8 && dma16); in isa_bus_dma()
110 assert(!bus->dma[0] && !bus->dma[1]); in isa_bus_dma()
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/qemu/docs/system/devices/
H A Dusb.rst25 therefore only a single USB bus) present in the system there is no
26 need to use the bus= parameter when adding USB devices.
35 because it provides a single USB bus supporting both USB 2.0 and USB
40 bus though, so there are two completely separate USB buses: One USB
41 1.1 bus driven by the UHCI controller and one USB 2.0 bus driven by
47 the PIIX3 chipset. The USB 1.1 bus will carry the name ``usb-bus.0``.
51 the controller so the USB 2.0 bus gets an individual name, for example
52 ``-device usb-ehci,id=ehci``. This will give you a USB 2.0 bus named
56 bus they should be attached to. Here is a complete example:
64 -device usb-tablet,bus=usb-bus.0 \\
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/qemu/hw/pci-bridge/
H A Dpci_expander_bridge.c32 #define TYPE_PXB_BUS "pxb-bus"
37 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
73 static int pxb_bus_num(PCIBus *bus) in pxb_bus_num() argument
75 PXBDev *pxb = PXB_DEV(bus->parent_dev); in pxb_bus_num()
80 static uint16_t pxb_bus_numa_node(PCIBus *bus) in pxb_bus_numa_node() argument
82 PXBDev *pxb = PXB_DEV(bus->parent_dev); in pxb_bus_numa_node()
132 PXBBus *bus = pci_bus_is_cxl(rootbus) ? in pxb_host_root_bus_path() local
137 snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus)); in pxb_host_root_bus_path()
138 return bus->bus_path; in pxb_host_root_bus_path()
152 pxb_bus = pxb_host->bus; in pxb_host_ofw_unit_address()
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/qemu/include/hw/pci/
H A Dpci_bus.h7 * PCI Bus datastructures.
18 int (*bus_num)(PCIBus *bus);
19 uint16_t (*numa_node)(PCIBus *bus);
23 /* This bus is the root of a PCI domain */
25 /* PCIe extended configuration space is accessible on this bus */
27 /* This is a CXL Type BUS */
52 /* The bus IRQ state is the logical OR of the connected devices.
60 static inline bool pci_bus_is_cxl(PCIBus *bus) in pci_bus_is_cxl() argument
62 return !!(bus->flags & PCI_BUS_CXL); in pci_bus_is_cxl()
65 static inline bool pci_bus_is_root(PCIBus *bus) in pci_bus_is_root() argument
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/qemu/include/hw/virtio/
H A Dvirtio-bus.h32 #define TYPE_VIRTIO_BUS "virtio-bus"
63 * This is called by virtio-bus just after the device is plugged.
68 * This is called by virtio-bus just before the device is unplugged.
119 void virtio_bus_reset(VirtioBusState *bus);
120 void virtio_bus_device_unplugged(VirtIODevice *bus);
122 uint16_t virtio_bus_get_vdev_id(VirtioBusState *bus);
124 size_t virtio_bus_get_vdev_config_len(VirtioBusState *bus);
126 uint32_t virtio_bus_get_vdev_bad_features(VirtioBusState *bus);
128 void virtio_bus_get_vdev_config(VirtioBusState *bus, uint8_t *config);
130 void virtio_bus_set_vdev_config(VirtioBusState *bus, uint8_t *config);
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