| /linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
[all …]
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| D | arm-pl08x.txt | 4 - compatible: "arm,pl080", "arm,primecell";
7 - arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
11 - reg: Address range of the PL08x registers
12 - interrupt: The PL08x interrupt number
13 - clocks: The clock running the IP core clock
14 - clock-names: Must contain "apb_pclk"
15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | ifm-csi.txt | 1 IFM camera sensor interface on mpc5200 LocalPlus bus
4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/media/ |
| D | ti,da850-vpif.txt | 2 ----------------------
12 - compatible: must be "ti,da850-vpif"
13 - reg: physical base address and length of the registers set for the device;
14 - interrupts: should contain IRQ line for the VPIF
18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
23 Documentation/devicetree/bindings/media/video-interfaces.txt.
25 Example using 2 8-bit input channels, one of which is connected to an
26 I2C-connected TVP5147 decoder:
29 compatible = "ti,da850-vpif";
[all …]
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| D | allwinner,sun6i-a31-csi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
19 - allwinner,sun8i-v3s-csi
[all …]
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| /linux-5.10/arch/sh/include/mach-se/mach/ |
| D | mrshpc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
19 * PC-Card window open in mrshpc_setup_windows()
25 /* common mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
28 /* common mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
34 /* attribute mode & bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
37 /* attribute mode & bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
44 __raw_writew(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ in mrshpc_setup_windows()
46 __raw_writew(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ in mrshpc_setup_windows()
|
| /linux-5.10/drivers/media/platform/xilinx/ |
| D | xilinx-vip.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include <dt-bindings/media/xilinx-vip.h>
20 #include "xilinx-vip.h"
22 /* -----------------------------------------------------------------------------
46 * xvip_get_format_by_code - Retrieve format information for a media bus code
47 * @code: the format media bus code
50 * given V4L2 media bus format @code, or ERR_PTR if no corresponding format can
60 if (format->code == code) in xvip_get_format_by_code()
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 1 Device tree bindings for NVIDIA Tegra Generic Memory Interface bus
3 The Generic Memory Interface bus enables memory transfers between internal and
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
14 LCDs that can display one or more lines of text. It exposes an M6800 bus
15 interface, which can be used in either 4-bit or 8-bit mode.
21 data-gpios:
23 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
24 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
26 - maxItems: 4
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | cavium-mmc.txt | 10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
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| D | atmel-hsmci.txt | 7 by mmc.txt and the properties used by the atmel-mci driver.
12 - compatible: should be "atmel,hsmci"
13 - #address-cells: should be one. The cell is the slot id.
14 - #size-cells: should be zero.
15 - at least one slot node
16 - clock-names: tuple listing input clock names.
18 - clocks: phandles to input clocks.
28 #address-cells = <1>;
29 #size-cells = <0>;
30 clock-names = "mci_clk";
[all …]
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| /linux-5.10/drivers/net/ethernet/intel/fm10k/ |
| D | fm10k_common.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 * fm10k_get_bus_info_generic - Generic set PCI bus info
10 * Gets the PCI bus info (speed, width, type) then calls helper function to
17 /* Get the maximum link width and speed from PCIe config space */ in fm10k_get_bus_info_generic()
22 hw->bus_caps.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
25 hw->bus_caps.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
28 hw->bus_caps.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
31 hw->bus_caps.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
34 hw->bus_caps.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
[all …]
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| /linux-5.10/arch/arm/boot/dts/ |
| D | imx6q-gw54xx.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
8 #include "imx6qdl-gw54xx.dtsi"
9 #include <dt-bindings/media/tda1997x.h>
13 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
15 sound-digital {
16 compatible = "simple-audio-card";
17 simple-audio-card,name = "tda1997x-audio";
18 simple-audio-card,format = "i2s";
19 simple-audio-card,bitclock-master = <&sound_codec>;
[all …]
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| D | s5pv210-torbreck.dts | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
12 * NOTE: This file is completely based on original board file for mach-torbreck
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
34 pmic_ap_clk: clock-0 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
43 clock-frequency = <24000000>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | i2c-ocores.txt | 1 Device tree configuration for i2c-ocores
4 - compatible : "opencores,i2c-ocores"
6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
10 - reg : bus address start and address range size of device
11 - clocks : handle to the controller clock; see the note below.
12 Mutually exclusive with opencores,ip-clock-frequency
13 - opencores,ip-clock-frequency: frequency of the controller clock in Hz;
15 - #address-cells : should be <1>
16 - #size-cells : should be <0>
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
5 such as ethernet controllers to processors using the TI GPMC as a data bus.
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
[all …]
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| /linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a-qds.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
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| D | fsl-lx2160a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
21 stdout-path = "serial0:115200n8";
24 sb_3v3: regulator-sb3v3 {
25 compatible = "regulator-fixed";
26 regulator-name = "MC34717-3.3VSB";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
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| D | fsl-ls208xa-qds.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 mmc-hs200-1_8v;
19 #address-cells = <2>;
20 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "cfi-flash";
30 bank-width = <2>;
31 device-width = <1>;
35 compatible = "fsl,ifc-nand";
[all …]
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| D | fsl-ls1088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
23 i2c-switch@77 {
26 #address-cells = <1>;
27 #size-cells = <0>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 shunt-resistor = <1000>;
[all …]
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| /linux-5.10/include/media/ |
| D | v4l2-mediabus.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Media Bus API header
11 #include <linux/v4l2-mediabus.h>
17 * bus configuration parameter. One and only one bit of each group of flags
20 * conflicting settings are specified when reporting and setting the media bus
62 /* FIELD = 0/1 - Field1 (odd)/Field2 (even) */
64 /* FIELD = 1/0 - Field1 (odd)/Field2 (even) */
66 /* Active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. */
73 /* CSI-2 D-PHY number of data lanes. */
78 /* CSI-2 Virtual Channel identifiers. */
[all …]
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| /linux-5.10/arch/arm64/boot/dts/xilinx/ |
| D | zynqmp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/ata/ |
| D | cavium-compact-flash.txt | 3 The Cavium Compact Flash device is connected to the Octeon Boot Bus,
4 and is thus a child of the Boot Bus device. It can read and write
8 - compatible: "cavium,ebt3000-compact-flash";
12 - reg: The base address of the CF chip select banks. Depending on
15 - cavium,bus-width: The width of the connection to the CF devices. Valid
18 - cavium,true-ide: Optional, if present the CF connection is in True IDE mode.
20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
24 compact-flash@5,0 {
25 compatible = "cavium,ebt3000-compact-flash";
27 cavium,bus-width = <16>;
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 1 * Boot Bus
3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
7 - compatible: "cavium,octeon-3860-bootbus"
11 - reg: The base address of the Boot Bus' register bank.
13 - #address-cells: Must be <2>. The first cell is the chip select
16 - #size-cells: Must be <1>.
18 - ranges: There must be one one triplet of (child-bus-address,
19 parent-bus-address, length) for each active chip select. If the
27 - compatible: "cavium,octeon-3860-bootbus-config"
29 - cavium,cs-index: A single cell indicating the chip select that
[all …]
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | atmel,ebi.txt | 3 The External Bus Interface (EBI) controller is a bus where you can connect
5 The EBI provides a glue-less interface to asynchronous memories through the SMC
10 - compatible: "atmel,at91sam9260-ebi"
11 "atmel,at91sam9261-ebi"
12 "atmel,at91sam9263-ebi0"
13 "atmel,at91sam9263-ebi1"
14 "atmel,at91sam9rl-ebi"
15 "atmel,at91sam9g45-ebi"
16 "atmel,at91sam9x5-ebi"
17 "atmel,sama5d3-ebi"
[all …]
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