| /linux-3.3/drivers/gpu/drm/nouveau/ |
| D | nouveau_calc.c | 38 int burst; member
105 fifo->burst = cbs; in nv04_calc_arb()
119 * to the CRTC FIFO burst. (ns) */ in nv10_calc_arb()
171 /* FIFO burst */ in nv10_calc_arb()
173 /* Max burst not leading to overflows. */ in nv10_calc_arb()
176 fifo->burst = min(max_burst_o, 1024); in nv10_calc_arb()
178 /* Max burst value with an acceptable latency. */ in nv10_calc_arb()
180 fifo->burst = min(max_burst_l, fifo->burst); in nv10_calc_arb()
182 fifo->burst = rounddown_pow_of_two(fifo->burst); in nv10_calc_arb()
187 max_lwm = fifo_len - fifo->burst in nv10_calc_arb()
[all …]
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| /linux-3.3/net/netfilter/ |
| D | xt_limit.c | 108 if (r->burst == 0 in limit_mt_check()
109 || user2credits(r->avg * r->burst) < user2credits(r->avg)) { in limit_mt_check()
111 r->avg, r->burst); in limit_mt_check()
125 priv->credit = user2credits(r->avg * r->burst); /* Credits full. */ in limit_mt_check()
126 r->credit_cap = user2credits(r->avg * r->burst); /* Credits full. */ in limit_mt_check()
142 u_int32_t burst; member
158 .burst = cm->burst, in limit_mt_compat_from_user()
172 .burst = m->burst, in limit_mt_compat_to_user()
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| /linux-3.3/net/bridge/netfilter/ |
| D | ebt_limit.c | 73 if (info->burst == 0 || in ebt_limit_mt_check()
74 user2credits(info->avg * info->burst) < user2credits(info->avg)) { in ebt_limit_mt_check()
76 info->avg, info->burst); in ebt_limit_mt_check()
82 info->credit = user2credits(info->avg * info->burst); in ebt_limit_mt_check()
83 info->credit_cap = user2credits(info->avg * info->burst); in ebt_limit_mt_check()
92 * only avg/burst have meaningful values in userspace.
95 compat_uint_t avg, burst; member
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| /linux-3.3/drivers/atm/ |
| D | Kconfig | 64 bool "Fine-tune burst settings"
69 transfer is called a burst.
71 The default settings for the burst sizes are suitable for most PCI
75 The burst sizes can be set independently in the send (TX) and
78 Note that enabling many different burst sizes in the same direction
81 available burst size.
91 Burst sixteen words at once in the send direction. This may work
98 Burst eight words at once in the send direction. This is the default
105 Burst four words at once in the send direction. You may want to try
113 Burst two words at once in the send direction. You may want to try
[all …]
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| D | uPD98401.h | 101 #define uPD98401_ADDR 0x05 /* Last Burst Address */
122 #define uPD98401_GMR_SZ 0x00000f00 /* Burst Size Enable */
123 #define uPD98401_BURST16 0x00000800 /* 16-word burst */
124 #define uPD98401_BURST8 0x00000400 /* 8-word burst */
125 #define uPD98401_BURST4 0x00000200 /* 4-word burst */
126 #define uPD98401_BURST2 0x00000100 /* 2-word burst */
127 #define uPD98401_GMR_AD 0x00000080 /* Address (burst resolution) Disable */
|
| /linux-3.3/include/linux/ |
| D | ratelimit.h | 14 int burst; member
25 .burst = burst_init, \
29 int interval, int burst) in ratelimit_state_init() argument
33 rs->burst = burst; in ratelimit_state_init()
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| D | intel_mid_dma.h | 45 /*Burst size configuration*/
63 * @src_msize: Source DMA burst size
64 * @dst_msize: Dst DMA burst size
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| /linux-3.3/arch/arm/plat-pxa/ |
| D | dma.c | 72 int burst = (dcmd >> 16) & 0x3; in dbg_burst_from_dcmd() local
74 return burst ? 4 << burst : 0; in dbg_burst_from_dcmd()
89 int i, max_show = 20, burst, width; in dbg_show_descriptors() local
103 burst = dbg_burst_from_dcmd(dcmd); in dbg_show_descriptors()
117 DCMD_STR(ENDIAN), burst, width, in dbg_show_descriptors()
138 int burst, width; in dbg_show_chan_state() local
143 burst = dbg_burst_from_dcmd(dcmd); in dbg_show_chan_state()
166 DCMD_STR(ENDIAN), burst, width, dcmd & DCMD_LENGTH); in dbg_show_chan_state()
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| /linux-3.3/arch/arm/mach-bcmring/include/mach/ |
| D | reg_umi.h | 89 /* Enable wait pin during burst write or read */
99 /* page size/burst size (wrap only) */
117 /* Page read access cycle / Burst write latency (n+2 / n+1) */
129 /* Read access cycle / Burst read latency (n+2 / n+1) */
145 /* Polarity of busy state of Burst Wait Signal */
147 /* Enable burst clock stopped when not accessing external burst flash/sram */
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| /linux-3.3/arch/mn10300/include/asm/ |
| D | busctl-regs.h | 65 #define BCBERR_BEBST_BURST 0x00000400 /* - burst */
99 #define SBCNTRL2_BWC 0x00000f00 /* burst wait count */
115 #define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */
116 #define SBCNTRL2_BTSE 0x80000000 /* burst enable */
128 #define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */
138 #define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */
|
| /linux-3.3/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac1000.h | 80 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
131 /* Programmable burst length (passed thorugh platform)*/
132 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
141 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
142 #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */
154 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */
|
| /linux-3.3/lib/ |
| D | ratelimit.c | 21 * This enforces a rate limit: not more than @rs->burst callbacks
56 if (rs->burst && rs->burst > rs->printed) { in ___ratelimit()
|
| /linux-3.3/include/media/ |
| D | upd64083.h | 41 /* YCS mode: Y/C separation (burst locked clocking) */
43 /* YCS+ mode: 2D Y/C separation and YCNR (burst locked clocking) */
50 /* YCNR mode: frame recursive YCNR (burst locked clocking) */
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| /linux-3.3/arch/sparc/include/asm/ |
| D | dma.h | 54 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
55 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
56 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
57 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
74 /* Values describing the burst-size property from the PROM */
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| /linux-3.3/arch/mips/cavium-octeon/executive/ |
| D | cvmx-pko.c | 442 * @burst: Maximum number of packets to burst in a row before rate
447 int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst) in cvmx_pko_rate_limit_packets() argument
462 ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8; in cvmx_pko_rate_limit_packets()
475 * @burst: Maximum number of bits to burst before rate
480 int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst) in cvmx_pko_rate_limit_bits() argument
501 pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256; in cvmx_pko_rate_limit_bits()
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| /linux-3.3/drivers/media/dvb/frontends/ |
| D | cx24116.c | 127 /* DiSEqC burst */
131 /* DiSEqC tone burst */
195 u8 burst; member
892 msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */ in cx24116_set_tone()
912 msleep(15); /* XXX determine is FW does this, see send_diseqc/burst */ in cx24116_set_tone()
941 /* DiSEqC burst */ in cx24116_diseqc_init()
959 /* Send DiSEqC message with derived burst (hack) || previous burst */
998 /* Message is sent without burst */ in cx24116_send_diseqc_msg()
1003 * Message is sent with derived else cached burst in cx24116_send_diseqc_msg()
1024 dprintk("%s burst=%d\n", __func__, in cx24116_send_diseqc_msg()
[all …]
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| /linux-3.3/arch/arm/mach-at91/include/mach/ |
| D | at91rm9200_mc.h | 134 /* Burst Flash Controller register */
136 #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
140 #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
155 #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
156 #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
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| /linux-3.3/arch/arm/mach-bcmring/include/mach/csp/ |
| D | dmacHw_reg.h | 250 #define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction len…
251 #define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */
252 #define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction len…
253 #define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction len…
254 #define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction len…
256 #define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */
257 #define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */
258 #define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4…
259 #define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8…
260 #define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 1…
[all …]
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| /linux-3.3/arch/arm/plat-pxa/include/plat/ |
| D | dma.h | 46 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
47 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
48 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
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| /linux-3.3/include/linux/netfilter/ |
| D | xt_hashlimit.h | 25 __u32 burst; /* Period multiplier for upper limit. */ member
49 __u32 burst; /* Period multiplier for upper limit. */ member
|
| /linux-3.3/include/linux/spi/ |
| D | pxa2xx_spi.h | 98 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
99 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
100 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
|
| /linux-3.3/Documentation/devicetree/bindings/c6x/ |
| D | emifa.txt | 20 - ti,emifa-burst-priority:
42 ti,emifa-burst-priority = <255>;
|
| /linux-3.3/arch/avr32/mach-at32ap/include/mach/ |
| D | hmatrix.h | 23 /* Undefined length burst limit */
32 # define HMATRIX_SCFG_SLOT_CYCLE(x) ((x) << 0) /* Max burst cycles */
|
| /linux-3.3/drivers/dma/ |
| D | pl330.c | 77 int burst_len; /* the number of burst */
598 /* Call after fixing burst size */
676 int burst; in pl330_prep_dma_memcpy() local
691 /* Select max possible burst size */ in pl330_prep_dma_memcpy()
692 burst = pi->pcfg.data_bus_width / 8; in pl330_prep_dma_memcpy()
694 while (burst > 1) { in pl330_prep_dma_memcpy()
695 if (!(len % burst)) in pl330_prep_dma_memcpy()
697 burst /= 2; in pl330_prep_dma_memcpy()
701 while (burst != (1 << desc->rqcfg.brst_size)) in pl330_prep_dma_memcpy()
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| /linux-3.3/sound/soc/kirkwood/ |
| D | kirkwood-dma.c | 137 /* Ensure that all constraints linked to dma burst are fulfilled */ in kirkwood_dma_open()
140 priv->burst * 2, in kirkwood_dma_open()
147 priv->burst); in kirkwood_dma_open()
153 priv->burst); in kirkwood_dma_open()
|