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/linux-6.15/drivers/fpga/tests/
Dfpga-bridge-test.c1 // SPDX-License-Identifier: GPL-2.0
3 * KUnit test for the FPGA Bridge
12 #include <linux/fpga/fpga-bridge.h>
17 bool enable; member
21 struct fpga_bridge *bridge; member
33 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
35 struct bridge_stats *stats = bridge->priv; in op_enable_set()
37 stats->enable = enable; in op_enable_set()
43 * Fake FPGA bridge that implements only the enable_set op to track
51 * register_test_bridge() - Register a fake FPGA bridge for testing.
[all …]
Dfpga-region-test.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/fpga/fpga-bridge.h>
13 #include <linux/fpga/fpga-mgr.h>
14 #include <linux/fpga/fpga-region.h>
23 bool enable; member
30 struct fpga_bridge *bridge; member
53 struct mgr_stats *stats = mgr->priv; in op_write()
55 stats->write_count++; in op_write()
70 static int op_enable_set(struct fpga_bridge *bridge, bool enable) in op_enable_set() argument
72 struct bridge_stats *stats = bridge->priv; in op_enable_set()
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/linux-6.15/drivers/fpga/
Daltera-hps2fpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
9 * Signed-off-by: Anatolij Gustschin <agust@denx.de>
19 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
23 #include <linux/fpga/fpga-bridge.h>
50 static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) in alt_hps2fpga_enable_show() argument
52 struct altera_hps2fpga_data *priv = bridge->priv; in alt_hps2fpga_enable_show()
54 return reset_control_status(priv->bridge_reset); in alt_hps2fpga_enable_show()
[all …]
Daltera-fpga2sdram.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
12 * The bridge contains 4 read ports, 4 write ports, and 6 command ports.
23 * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
26 #include <linux/fpga/fpga-bridge.h>
56 static int alt_fpga2sdram_enable_show(struct fpga_bridge *bridge) in alt_fpga2sdram_enable_show() argument
58 struct alt_fpga2sdram_data *priv = bridge->priv; in alt_fpga2sdram_enable_show()
61 regmap_read(priv->sdrctl, ALT_SDR_CTL_FPGAPORTRST_OFST, &value); in alt_fpga2sdram_enable_show()
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Daltera-freeze-bridge.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Freeze Bridge Controller
13 #include <linux/fpga/fpga-bridge.h>
35 bool enable; member
44 struct device *dev = priv->dev; in altera_freeze_br_req_ack()
45 void __iomem *csr_illegal_req_addr = priv->base_addr + in altera_freeze_br_req_ack()
48 int ret = -ETIMEDOUT; in altera_freeze_br_req_ack()
62 ret = -EINVAL; in altera_freeze_br_req_ack()
66 status = readl(priv->base_addr + FREEZE_CSR_STATUS_OFFSET); in altera_freeze_br_req_ack()
70 ctrl = readl(priv->base_addr + FREEZE_CSR_CTRL_OFFSET); in altera_freeze_br_req_ack()
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Dfpga-bridge.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Bridge Framework Driver
5 * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
8 #include <linux/fpga/fpga-bridge.h>
23 * fpga_bridge_enable - Enable transactions on the bridge
25 * @bridge: FPGA bridge
29 int fpga_bridge_enable(struct fpga_bridge *bridge) in fpga_bridge_enable() argument
31 dev_dbg(&bridge->dev, "enable\n"); in fpga_bridge_enable()
33 if (bridge->br_ops->enable_set) in fpga_bridge_enable()
34 return bridge->br_ops->enable_set(bridge, 1); in fpga_bridge_enable()
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
52 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
100 tristate "Technologic Systems TS-73xx SBC FPGA Manager"
104 present on the TS-73xx SBC boards.
107 tristate "FPGA Bridge Framework"
116 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
120 tristate "Altera FPGA Freeze Bridge"
123 Say Y to enable drivers for Altera FPGA Freeze bridges. A
124 freeze bridge is a bridge that exists in the FPGA fabric to
133 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
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/linux-6.15/drivers/gpu/drm/bridge/
Dti-tdp158.c1 // SPDX-License-Identifier: GPL-2.0-only
13 struct drm_bridge bridge; member
15 struct gpio_desc *enable; // Operation Enable - pin 36 member
21 static void tdp158_enable(struct drm_bridge *bridge, in tdp158_enable() argument
25 struct tdp158 *tdp158 = bridge->driver_private; in tdp158_enable()
27 err = regulator_enable(tdp158->vcc); in tdp158_enable()
29 dev_err(tdp158->dev, "failed to enable vcc: %d", err); in tdp158_enable()
31 err = regulator_enable(tdp158->vdd); in tdp158_enable()
33 dev_err(tdp158->dev, "failed to enable vdd: %d", err); in tdp158_enable()
35 gpiod_set_value_cansleep(tdp158->enable, 1); in tdp158_enable()
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Dsimple-bridge.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Free Electrons
4 * Copyright (C) 2015-2016 NextThing Co
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
29 struct drm_bridge bridge; member
36 struct gpio_desc *enable; member
40 drm_bridge_to_simple_bridge(struct drm_bridge *bridge) in drm_bridge_to_simple_bridge() argument
42 return container_of(bridge, struct simple_bridge, bridge); in drm_bridge_to_simple_bridge()
57 if (sbridge->next_bridge->ops & DRM_BRIDGE_OP_EDID) { in simple_bridge_get_modes()
58 drm_edid = drm_bridge_edid_read(sbridge->next_bridge, connector); in simple_bridge_get_modes()
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Dti-dlpc3433.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <linux/media-bus-format.h>
31 WR_RGB_LED_EN = 0x52, /* Write RGB LED Enable */
36 WR_DSI_PORT_EN = 0xD7, /* Write DSI Port Enable */
57 struct drm_bridge bridge; member
70 static inline struct dlpc *bridge_to_dlpc(struct drm_bridge *bridge) in bridge_to_dlpc() argument
72 return container_of(bridge, struct dlpc, bridge); in bridge_to_dlpc()
107 static void dlpc_atomic_enable(struct drm_bridge *bridge, in dlpc_atomic_enable() argument
110 struct dlpc *dlpc = bridge_to_dlpc(bridge); in dlpc_atomic_enable()
111 struct device *dev = dlpc->dev; in dlpc_atomic_enable()
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Dmicrochip-lvds.c1 // SPDX-License-Identifier: GPL-2.0-only
60 struct drm_bridge bridge; member
64 static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) in bridge_to_lvds() argument
66 return container_of(bridge, struct mchp_lvds, bridge); in bridge_to_lvds()
71 return readl_relaxed(lvds->regs + offset); in lvds_readl()
76 writel_relaxed(val, lvds->regs + offset); in lvds_writel()
90 dev_err(lvds->dev, "%s: timeout error\n", __func__); in lvds_serialiser_on()
102 /* Enable the LVDS serializer */ in lvds_serialiser_on()
106 static int mchp_lvds_attach(struct drm_bridge *bridge, in mchp_lvds_attach() argument
109 struct mchp_lvds *lvds = bridge_to_lvds(bridge); in mchp_lvds_attach()
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Dite-it66121.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2018-2019, Artem Mygaiev
10 #include <linux/media-bus-format.h>
30 #include <sound/hdmi-codec.h>
299 struct drm_bridge bridge; member
341 gpiod_set_value(ctx->gpio_reset, 1); in it66121_hw_reset()
343 gpiod_set_value(ctx->gpio_reset, 0); in it66121_hw_reset()
348 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); in it66121_preamble_ddc()
353 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); in it66121_fire_afe()
362 if (ctx->bus_width == 12) in it66121_configure_input()
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/linux-6.15/include/drm/
Ddrm_bridge.h49 * enum drm_bridge_attach_flags - Flags for &drm_bridge_funcs.attach
53 * @DRM_BRIDGE_ATTACH_NO_CONNECTOR: When this flag is set the bridge
60 * struct drm_bridge_funcs - drm_bridge control functions
66 * This callback is invoked whenever our bridge is being attached to a
76 int (*attach)(struct drm_bridge *bridge,
82 * This callback is invoked whenever our bridge is being detached from a
87 void (*detach)(struct drm_bridge *bridge);
93 * bridge. This should be implemented if the bridge has some sort of
94 * restriction in the modes it can display. For example, a given bridge
111 * to look at anything else but the passed-in mode, and validate it
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/linux-6.15/drivers/gpu/drm/bridge/imx/
DKconfig10 This is a DRM bridge implementation for the DRM i.MX IPUv3 driver,
13 Newer designs should not use this bridge and should use proper panel
17 tristate "Freescale i.MX8MP HDMI-TX bridge support"
24 Choose this to enable support for the internal HDMI encoder found
28 tristate "Freescale i.MX8MP HDMI PVI bridge support"
31 Choose this to enable support for the internal HDMI TX Parallel
35 tristate "Freescale i.MX8QM LVDS display bridge"
41 Choose this to enable the internal LVDS Display Bridge(LDB) found in
45 tristate "Freescale i.MX8QXP LVDS display bridge"
51 Choose this to enable the internal LVDS Display Bridge(LDB) found in
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/linux-6.15/Documentation/devicetree/bindings/fpga/
Dfpga-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Bridge
10 - Michal Simek <michal.simek@amd.com>
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
16 bridge-enable:
18 0 if driver should disable bridge at startup
19 1 if driver should enable bridge at startup
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Daltr,freeze-bridge-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Freeze Bridge Controller
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
12 changes from passing through the bridge. The controller can also
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
17 - Xu Yilun <yilun.xu@intel.com>
20 - $ref: fpga-bridge.yaml#
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/linux-6.15/drivers/gpu/drm/
Ddrm_bridge.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 #include <linux/media-bus-format.h>
47 * A bridge is always attached to a single &drm_encoder at a time, but can be
50 * [ CRTC ---> ] Encoder ---> Bridge A ---> Bridge B
52 * Here, the output of the encoder feeds to bridge A, and that furthers feeds to
53 * bridge B. Bridge chains can be arbitrarily long, and shall be fully linear:
54 * Chaining multiple bridges to the output of a bridge, or the same bridge to
66 * Display drivers are responsible for linking encoders with the first bridge
67 * in the chains. This is done by acquiring the appropriate bridge with
68 * devm_drm_of_get_bridge(). Once acquired, the bridge shall be attached to the
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/linux-6.15/Documentation/devicetree/bindings/ata/
Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
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/linux-6.15/drivers/staging/vme_user/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 bool "VME bridge support"
6 Enable support for VME (VersaModular Eurocard bus) bridge modules.
7 The bridge allows connecting VME devices to systems with existing
11 Note that this only enables the bridge framework. You'll also
12 likely want to enable driver for specific bridge device you have
17 comment "VME Bridge Drivers"
20 tristate "Tundra TSI148 VME bridge support"
23 If you say Y here you get support for the Tundra TSI148 VME-to-PCI/X
24 bridge chip (and pin-compatible clones).
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Dvme_tsi148.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for the Tundra TSI148 VME-PCI Bridge Chip
20 #include <linux/dma-mapping.h>
74 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, in tsi148_DMA_irqhandler() argument
80 wake_up(&bridge->dma_queue[0]); in tsi148_DMA_irqhandler()
84 wake_up(&bridge->dma_queue[1]); in tsi148_DMA_irqhandler()
94 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) in tsi148_LM_irqhandler() argument
101 /* We only enable interrupts if the callback is set */ in tsi148_LM_irqhandler()
102 bridge->lm_callback[i](bridge->lm_data[i]); in tsi148_LM_irqhandler()
120 struct tsi148_driver *bridge; in tsi148_MB_irqhandler() local
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/linux-6.15/drivers/media/usb/gspca/m5602/
Dm5602_ov9650.c1 // SPDX-License-Identifier: GPL-2.0-only
25 {BRIDGE, M5602_XB_MCU_CLK_DIV, 0x02},
26 {BRIDGE, M5602_XB_MCU_CLK_CTRL, 0xb0},
27 {BRIDGE, M5602_XB_SEN_CLK_DIV, 0x00},
28 {BRIDGE, M5602_XB_SEN_CLK_CTRL, 0xb0},
29 {BRIDGE, M5602_XB_ADC_CTRL, 0xc0},
30 {BRIDGE, M5602_XB_SENSOR_CTRL, 0x00},
32 {BRIDGE, M5602_XB_SENSOR_TYPE, 0x08},
33 {BRIDGE, M5602_XB_GPIO_DIR, 0x05},
34 {BRIDGE, M5602_XB_GPIO_DAT, 0x04},
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/linux-6.15/tools/testing/selftests/net/forwarding/
Dbridge_vlan_mcast.sh2 # SPDX-License-Identifier: GPL-2.0
40 ip link add dev br0 type bridge mcast_snooping 1 mcast_querier 1 vlan_filtering 1
52 bridge vlan add vid 10-11 dev $swp1 master
53 bridge vlan add vid 10-11 dev $swp2 master
55 ip link set dev br0 type bridge mcast_vlan_snooping 1
56 check_err $? "Could not enable global vlan multicast snooping"
57 log_test "Vlan multicast snooping enable"
108 bridge -j mdb show dev br0 |
109 jq -e ".[].mdb[] | select(.grp == \"$TEST_GROUP\" and .vid == 10)" &>/dev/null
110 if [ $expect -eq 0 ]; then
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/linux-6.15/drivers/gpu/drm/mcde/
Dmcde_drv.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 * DOC: ST-Ericsson MCDE Driver
11 * The MCDE (short for multi-channel display engine) is a graphics
15 * ST-Ericsson U8500 where is was used for mass-market deployments
18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
25 * Memory -> Overlay -> Channel -> FIFO -> 8 formatters -> DSI/DPI
26 * External 0..5 0..3 A,B, 6 x DSI bridge
41 * helpers. We then provide a bridge to the DSI port, and on the DSI port
42 * bridge we connect hang a panel bridge or other bridge. This may be subject
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/linux-6.15/tools/testing/selftests/net/
Dtest_bridge_neigh_suppress.sh2 # SPDX-License-Identifier: GPL-2.0
4 # This test is for checking bridge neighbor suppression functionality. The
6 # host is connected to each bridge over multiple VLANs. The test checks that
10 # +-----------------------+ +------------------------+
22 # +----|------------------+ +----|-------------------+
25 # +----|-------------------------------+ +----|-------------------------------+
29 # | +------------+-----------+ | | +------------+-----------+ |
32 # | +---+---+ | | +---+---+ |
43 # | veth0 +-------+ veth0 |
46 # +------------------------------------+ +------------------------------------+
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/linux-6.15/drivers/gpu/drm/mediatek/
Dmtk_dpi.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/media-bus-format.h>
18 #include <linux/soc/mediatek/mtk-mmsys.h>
67 struct drm_bridge bridge; member
92 return container_of(b, struct mtk_dpi, bridge); in bridge_to_dpi()
127 * struct mtk_dpi_conf - Configuration of mediatek dpi.
128 * @dpi_factor: SoC-specific pixel clock PLL factor values.
132 * @edge_sel_en: Enable of edge selection.
142 * @yuv422_en_bit: Enable bit of yuv422.
143 * @csc_enable_bit: Enable bit of CSC.
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