Home
last modified time | relevance | path

Searched +full:bit +full:- +full:manipulation (Results 1 – 25 of 193) sorted by relevance

12345678

/linux-6.8/include/linux/
Dsysv_fs.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 /* inode numbers are 16 bit */
16 /* Block numbers are 24 bit, sometimes stored in 32 bit.
17 On Coherent FS, they are always stored in PDP-11 manner: the least
21 /* 0 is non-existent */
26 /* Xenix super-block data on disk */
39 char s_flock; /* lock during free block list manipulation */
40 char s_ilock; /* lock during inode cache manipulation */
41 char s_fmod; /* super-block modified flag */
42 char s_ronly; /* flag whether fs is mounted read-only */
[all …]
Dassoc_array.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * See Documentation/core-api/assoc_array.rst for information.
28 * Operations on objects and index keys for use by array manipulation routines.
31 /* Method to get a chunk of an index key from caller-supplied data */
40 /* How different is an object from an index key, to a bit position in
41 * their keys? (or -1 if they're the same)
50 * Access and manipulation functions.
56 array->root = NULL; in assoc_array_init()
57 array->nr_leaves_on_tree = 0; in assoc_array_init()
/linux-6.8/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
[all …]
/linux-6.8/Documentation/arch/riscv/
Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
[all …]
/linux-6.8/arch/nios2/platform/
DKconfig.platform1 # SPDX-License-Identifier: GPL-2.0-only
23 Normally this address is passed by a bootloader such as u-boot but
67 instruction. This will enable the -mhw-mul compiler flag.
73 instruction. Enables the -mhw-mulx compiler flag.
79 instruction. Enables the -mhw-div compiler flag.
86 the BMX Bit Manipulation Extension instructions. Enables
87 the -mbmx compiler flag.
94 the CDX Bit Manipulation Extension instructions. Enables
95 the -mcdx compiler flag.
100 Enables the -mcustom-fpu-cfg=60-1 compiler flag.
[all …]
/linux-6.8/fs/xfs/libxfs/
Dxfs_bit.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * XFS bit manipulation routines.
14 * masks with n high/low bits set, 64-bit values
18 return (uint64_t)-1 << (64 - (n)); in xfs_mask64hi()
22 return ((uint32_t)1 << (n)) - 1; in xfs_mask32lo()
26 return ((uint64_t)1 << (n)) - 1; in xfs_mask64lo()
29 /* Get high bit set out of 32-bit argument, -1 if none set */
32 return fls(v) - 1; in xfs_highbit32()
35 /* Get high bit set out of 64-bit argument, -1 if none set */
38 return fls64(v) - 1; in xfs_highbit64()
[all …]
Dxfs_bit.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2005 Silicon Graphics, Inc.
11 * XFS bit manipulation routines, used in non-realtime code.
17 * Returns 1 for empty, 0 for non-empty.
33 * Count the number of contiguous bits set in the bitmap starting with bit
46 size -= start_bit & ~(NBWORD - 1); in xfs_contig_bits()
47 start_bit &= (NBWORD - 1); in xfs_contig_bits()
51 tmp |= (~0U >> (NBWORD-start_bit)); in xfs_contig_bits()
55 size -= NBWORD; in xfs_contig_bits()
61 size -= NBWORD; in xfs_contig_bits()
[all …]
/linux-6.8/include/uapi/linux/
Dcapability.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
11 * ftp://www.kernel.org/pub/linux/libs/security/linux-privs/kernel-2.6/
19 /* User-level do most of the mapping between kernel and user
33 #define _LINUX_CAPABILITY_VERSION_2 0x20071026 /* deprecated - use v3 */
96 * Backwardly compatible definition for source code - trapped in a
97 * 32-bit world. If you find you need this, please consider using
107 ** POSIX-draft defined capabilities.
138 the S_ISGID bit on that file; that the S_ISUID and S_ISGID bits are
149 /* Allows setgid(2) manipulation */
155 /* Allows set*uid(2) manipulation (including fsuid). */
[all …]
/linux-6.8/arch/arm64/kvm/hyp/include/hyp/
Dadjust_pc.h1 // SPDX-License-Identifier: GPL-2.0-only
3 * Guest PC manipulation helpers
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Copyright (C) 2020 - Google LLC
36 vcpu_gp_regs(vcpu)->pstate = read_sysreg_el2(SYS_SPSR); in __kvm_skip_instr()
40 write_sysreg_el2(vcpu_gp_regs(vcpu)->pstate, SYS_SPSR); in __kvm_skip_instr()
46 * Assumes host is always 64-bit.
/linux-6.8/drivers/net/dsa/mv88e6xxx/
Dserdes.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
21 #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
22 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
23 #define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
24 #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
25 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
26 #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
27 #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
28 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
[all …]
/linux-6.8/drivers/gpio/
Dgpio-xtensa.c1 // SPDX-License-Identifier: GPL-2.0
12 * GPIO32 option is implemented as 32bit Tensilica Instruction Extension (TIE)
13 * output state called EXPSTATE, and 32bit input wire called IMPWIRE. This
18 * disables access to all coprocessors. This driver sets the CPENABLE bit
25 * would need to have a per core workqueue to do the actual GPIO manipulation.
48 xtensa_set_sr(*cpenable | BIT(XCHAL_CP_ID_XTIOP), cpenable); in enable_cp()
86 return !!(impwire & BIT(offset)); in xtensa_impwire_get_value()
109 return !!(expstate & BIT(offset)); in xtensa_expstate_get_value()
116 u32 mask = BIT(offset); in xtensa_expstate_set_value()
117 u32 val = value ? BIT(offset) : 0; in xtensa_expstate_set_value()
[all …]
/linux-6.8/fs/ocfs2/
Dalloc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
21 * the b-tree operations in ocfs2. Now all the b-tree operations are not
23 * to store can use b-tree. And it only needs to implement its ocfs2_extent_tree
26 * ocfs2_extent_tree becomes the first-class object for extent tree
27 * manipulation. Callers of the alloc.c code need to fill it via one of
30 * ocfs2_extent_tree contains info for the root of the b-tree, it must have a
31 * root ocfs2_extent_list and a root_bh so that they can be used in the b-tree
37 * the root of extent b-tree.
138 * of extent tree. So for an inode, it should be &fe->id2.i_list. Otherwise
149 * top-of-the tree. in ocfs2_extend_meta_needed()
[all …]
/linux-6.8/fs/xfs/
Dxfs_bmap_util.h1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2000-2006 Silicon Graphics, Inc.
29 return -EFSCORRUPTED; in xfs_bmap_rtalloc()
38 __s64 bmv_block; /* starting block (64-bit daddr_t) */
65 /* EOF block manipulation functions */
/linux-6.8/include/linux/soc/ti/
Dknav_dma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * PKTDMA descriptor manipulation macros for host packet descriptor
17 #define MASK(x) (BIT(x) - 1)
20 #define KNAV_DMA_DESC_PS_INFO_IN_SOP BIT(22)
27 #define KNAV_DMA_DESC_HAS_EPIB BIT(31)
175 return -EINVAL; in knav_dma_get_flow()
/linux-6.8/tools/arch/x86/include/asm/
Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 21 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
22 * this feature bit is not displayed in /proc/cpuinfo at all.
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
[all …]
/linux-6.8/arch/x86/include/asm/
Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 21 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
22 * this feature bit is not displayed in /proc/cpuinfo at all.
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* 36-bit PSEs */
[all …]
Dpgtable-2level.h1 /* SPDX-License-Identifier: GPL-2.0 */
52 return __pte(xchg(&xp->pte_low, 0)); in native_ptep_get_and_clear()
76 /* Bit manipulation helper on pte/pgoff entry */
91 * <----------------- offset ------------------> 0 E <- type --> 0
96 #define _SWP_TYPE_MASK ((1U << SWP_TYPE_BITS) - 1)
111 /* We borrow bit 7 to store the exclusive marker in swap PTEs. */
/linux-6.8/security/
DKconfig.hardening1 # SPDX-License-Identifier: GPL-2.0-only
12 flaws, this plugin is available to identify and zero-initialize
23 def_bool $(cc-option,-ftrivial-auto-var-init=pattern)
26 def_bool $(cc-option,-ftrivial-auto-var-init=zero)
29 # Clang 16 and later warn about using the -enable flag, but it
31 …def_bool $(cc-option,-ftrivial-auto-var-init=zero -enable-trivial-auto-var-init-zero-knowing-it-wi…
64 bool "zero-init structs marked for userspace (weak)"
69 Zero-initialize any structures on the stack containing
72 exposures, like CVE-2013-2141:
76 bool "zero-init structs passed by reference (strong)"
[all …]
/linux-6.8/drivers/mtd/chips/
Dfwh_lock.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 struct cfi_private *cfi = map->fldrv_priv; in fwh_xxlock_oneblock()
37 if (chip->start < 0x400000) { in fwh_xxlock_oneblock()
38 pr_debug( "MTD %s(): chip->start: %lx wanted >= 0x400000\n", in fwh_xxlock_oneblock()
39 __func__, chip->start ); in fwh_xxlock_oneblock()
40 return -EIO; in fwh_xxlock_oneblock()
44 * - on 64k boundariesand in fwh_xxlock_oneblock()
45 * - bit 1 set high in fwh_xxlock_oneblock()
46 * - block lock registers are 4MiB lower - overflow subtract (danger) in fwh_xxlock_oneblock()
48 * The address manipulation is first done on the logical address in fwh_xxlock_oneblock()
[all …]
/linux-6.8/fs/btrfs/
Dextent-io-tree.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 * Bit not representing a state but a request for NOWAIT semantics,
66 * / EXTENT_CLEAR_DATA_RESV because they have special meaning to the bit
67 * manipulation functions
94 * owner == IO_TREE_INODE_IO - then inode is valid and fs_info can be
95 * accessed as inode->root->fs_info
146 bool test_range_bit(struct extent_io_tree *tree, u64 start, u64 end, u32 bit,
148 bool test_range_bit_exists(struct extent_io_tree *tree, u64 start, u64 end, u32 bit);
/linux-6.8/drivers/input/mouse/
Dtrackpoint.h1 /* SPDX-License-Identifier: GPL-2.0-only */
47 * Mode manipulation
67 #define TP_REACH 0x57 /* Backup for Z-axis press */
70 /* with Z-axis pressed) */
75 #define TP_THRESH 0x5C /* Minimum value for a Z-axis press */
76 #define TP_UP_THRESH 0x5A /* Used to generate a 'click' on Z-axis */
106 #define TP_TOGGLE_SOURCE_TAG 0x20 /* Bit 3 of the first packet will be set to
109 #define TP_TOGGLE_EXT_TAG 0x22 /* Bit 3 of the first packet coming from the
/linux-6.8/include/net/
Dneighbour.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Generic neighbour manipulation
17 * - Add neighbour cache statistics like rtstat
93 set_bit(index, p->data_state); in neigh_var_set()
94 p->data[index] = val; in neigh_var_set()
97 #define NEIGH_VAR(p, attr) ((p)->data[NEIGH_VAR_ ## attr])
107 bitmap_fill(p->data_state, NEIGH_VAR_DATA_MAX); in neigh_parms_data_state_setall()
112 bitmap_zero(p->data_state, NEIGH_VAR_DATA_MAX); in neigh_parms_data_state_cleanall()
135 #define NEIGH_CACHE_STAT_INC(tbl, field) this_cpu_inc((tbl)->stats->field)
187 * neighbour table manipulation
[all …]
/linux-6.8/net/sched/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
25 To administer these schedulers, you'll need the user-level utilities
54 in-depth articles.
74 Say Y here if you want to use an n-band priority queue packet
81 tristate "Hardware Multiqueue-aware Multi Band Queuing (MULTIQ)"
83 Say Y here if you want to use an n-band queue packet scheduler
199 re-ordering. This is often useful to simulate networks when
219 tristate "Multi-queue priority scheduler (MQPRIO)"
222 Say Y here if you want to use the Multi-queue Priority scheduler.
235 scheduler. This schedules packets according to skb->priority,
[all …]
/linux-6.8/drivers/ptp/
Dptp_mock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Mock-up PTP Hardware Clock driver for virtual network devices
7 * Create a PTP clock which offers PTP time manipulation operations
15 /* Clamp scaled_ppm between -2,097,152,000 and 2,097,152,000,
16 * and thus "adj" between -68,719,476 and 68,719,476
29 * 64-bit overflow during the multiplication with cc->mult, given the max "adj"
57 spin_lock(&phc->lock); in mock_phc_adjfine()
58 timecounter_read(&phc->tc); in mock_phc_adjfine()
59 phc->cc.mult = MOCK_PHC_CC_MULT + adj; in mock_phc_adjfine()
60 spin_unlock(&phc->lock); in mock_phc_adjfine()
[all …]
/linux-6.8/arch/alpha/kernel/
Dpci_impl.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 * may also have PCI-PCI bridges present, and then we'd configure the
31 * a single bit set. This is so that devices like the broken Myrinet card
38 * that get passed through the PCI<->ISA bridge chip. Although this causes
39 * us to set the PCI->Mem window bases lower than normal, we still allocate
47 #define XL_DEFAULT_MEM_BASE ((16+2)*1024*1024) /* 16M to 64M-1 is avail */
59 * avoid the HAE manipulation that would be needed.
73 #define IRONGATE_DEFAULT_MEM_BASE ((256*8-16)*1024*1024)
79 * later) adheres to the PCI-PCI bridge specification. This says that
108 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
[all …]

12345678