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/linux-6.8/Documentation/devicetree/bindings/gpio/
Dgpio-mmio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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Dbrcm,bcm63xx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,bcm63xx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM63xx GPIO controller
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Bindings for Broadcom's BCM63xx memory-mapped GPIO controllers.
16 These bindings can be used on any BCM63xx SoC. However, BCM6338 and BCM6345
19 BCM6338 have 8-bit data and dirout registers, where GPIO state can be read
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/linux-6.8/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm4908.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
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/linux-6.8/drivers/irqchip/
DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_IRQCHIP) += irqchip.o
4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o
5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o
8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
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/linux-6.8/drivers/gpio/
Dgpio-mmio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Generic driver for memory-mapped GPIO controllers.
10 * ..The simplest form of a GPIO controller that the driver supports is``
11 * `.just a single "data" register, where GPIO state can be read and/or `
16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
22 * . big-endian notation, just`. .. A bit more sophisticated controllers ,
23 * . register the device with -be`. .with a pair of set/clear-bit registers ,
29 * .. The expectation is that in at least some cases . ,-~~~-,
30 * .this will be used with roll-your-own ASIC/FPGA .` \ /
58 #include <linux/gpio/driver.h>
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/linux-6.8/arch/mips/include/asm/mach-bcm63xx/
Dbcm63xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* BCM6345 clock bits are shifted by 16 on the left, because of the test
91 * control register which is 16-bits wide. That way we do not have any
92 * specific BCM6345 code for handling clocks, and writing 0 to the test
470 /* GPIO registers */
477 /* GPIO mux registers and constants */
549 /* those bits must be kept as read in gpio basemode register*/
996 /* Endpoint<->DMA mappings */
1003 /* Misc per-endpoint settings */
1267 #define SPI_6348_CMD 0x00 /* 16-bits register */
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