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/qemu/pc-bios/dtb/
H A Dpetalogix-ml605.dts22 ethernet0 = "/axi/axi-ethernet@82780000";
23 serial0 = "/axi/serial@83e00000";
28 stdout-path = "/axi/serial@83e00000";
57 xlnx,d-axi = < 0x01 >;
84 xlnx,i-axi = < 0x01 >;
134 axi {
137 compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus";
140 axi-ethernet@82780000 {
142 compatible = "xlnx,axi-ethernet-2.01.a\0xlnx,axi-ethernet-1.00.a";
180 axi_dma: axi-dma@84600000 {
[all …]
/qemu/docs/system/riscv/
H A Dmicroblaze-v-generic.rst19 - axi emac
20 - axi dma
/qemu/hw/riscv/
H A Dmicroblaze-v-generic.c134 /* axi ethernet and dma initialization. */ in mb_v_generic_init()
135 eth0 = qdev_new("xlnx.axi-ethernet"); in mb_v_generic_init()
136 dma = qdev_new("xlnx.axi-dma"); in mb_v_generic_init()
/qemu/hw/dma/
H A Dxilinx_axidma.c2 * QEMU model of Xilinx AXI-DMA block.
43 #define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
44 #define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
45 #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
424 hw_error("AXI DMA requires %d byte control stream payload\n", in xilinx_axidma_control_stream_push()
610 "xlnx.axi-dma", R_MAX * 4 * 2); in xilinx_axidma_init()
H A Dxlnx_csu_dma.c697 * Data width in bits of the AXI S2MM AXI4-Stream Data bus.
/qemu/hw/microblaze/
H A Dpetalogix_ml605_mmu.c137 /* axi ethernet and dma initialization. */ in petalogix_ml605_init()
138 eth0 = qdev_new("xlnx.axi-ethernet"); in petalogix_ml605_init()
139 dma = qdev_new("xlnx.axi-dma"); in petalogix_ml605_init()
/qemu/hw/misc/
H A Da9scu.c36 /* RAZ/WI, like an implementation with only one AXI master */ in a9_scu_read()
67 /* RAZ/WI, like an implementation with only one AXI master */ in a9_scu_write()
H A Dallwinner-h3-ccu.c39 REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
H A Dmchp_pfsoc_ioscb.c33 * named as "System Port 0 (AXI-D0)".
/qemu/hw/arm/
H A Dvexpress.c311 /* 0x10060000 AXI RAM */ in a9_daughterboard_init()
319 /* 0x100e9000 PL301 'Fast' AXI matrix */ in a9_daughterboard_init()
320 /* 0x100ea000 PL301 'Slow' AXI matrix */ in a9_daughterboard_init()
341 45000000, /* AMBA AXI ACLK: 45MHz */
388 /* 0x2a000000: PL301 AXI interconnect: not modelled */ in a15_daughterboard_init()
412 40000000, /* OSCCLK4: 40MHz : external AXI master clock */
/qemu/hw/net/
H A Dxgmac.c4 * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
81 #define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */
82 #define DMA_AXI_STATUS 0x000003cb /* AXI Status */
H A Dxilinx_axienet.c2 * QEMU model of Xilinx AXI-Ethernet.
41 #define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
863 hw_error("AXI Enet requires %d byte control stream payload\n", in xilinx_axienet_control_stream_push()
957 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", in xilinx_enet_realize()
961 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet", in xilinx_enet_realize()
/qemu/include/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.h41 * + sysbus IRQ 0: PMC (AXI and APB) parity error interrupt detected by the PMC
H A Daspeed_scu.h284 * 11:9 AXI/AHB clock frequency ratio selection
/qemu/docs/system/arm/
H A Dvexpress.rst35 - PL301 AXI interconnect
/qemu/hw/pci-host/
H A Dxilinx-pcie.c295 dc->desc = "Xilinx AXI-PCIe Host Bridge"; in xilinx_pcie_root_class_init()
H A Ddesignware.c85 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
/qemu/hw/intc/
H A Dbcm2836_control.c9 * not PMU interrupt, or AXI counters).
/qemu/target/xtensa/core-de212/
H A Dcore-isa.h254 #define XCHAL_HAVE_AXI 0 /* AXI bus */
255 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h269 #define XCHAL_HAVE_AXI 0 /* AXI bus */
270 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h347 #define XCHAL_HAVE_AXI 0 /* AXI bus */
348 #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
/qemu/hw/ssi/
H A Dxilinx_spips.c1245 * - AXI writes generate an external AXI slave error (SLVERR) in lqspi_write()
/qemu/hw/usb/
H A Dhcd-dwc3.c5 * registers control the AXI/AHB interfaces properties, external FIFO support
/qemu/hw/mips/
H A Dboston.c469 "xlnx,axi-pcie-host-1.00.a"); in fdt_create_pcie()
/qemu/target/microblaze/
H A Dtranslate.c866 /* No support for AXI exclusive so always clear C */ in trans_lwx()
1555 /* Insns connected to FSL or AXI stream attached devices. */

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