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/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2010 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
54 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
106 * Specific encoded cache attribute values of general interest.
112 #define XCHAL_CA_WRITETHRU 1 /* cache enabled (write-through) mode */
[all …]
/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h2 * xtensa/config/core-matmap.h -- Memory access and translation mapping
10 * information contained in the core-isa.h header file.
19 * XCHAL_ICACHE_SIZE (presence of I-cache)
20 * XCHAL_DCACHE_SIZE (presence of D-cache)
25 /* Copyright (c) 1999-2020 Tensilica Inc.
49 /*----------------------------------------------------------------------
51 ----------------------------------------------------------------------*/
55 /* Cache Attribute encodings -- lists of access modes for each cache attribute: */
111 * Specific encoded cache attribute values of general interest.
117 #define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
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H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2020 Tensilica Inc.
34 //depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
46 /*----------------------------------------------------------------------
48 ----------------------------------------------------------------------*/
50 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
56 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
57 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
58 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
69 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
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/qemu/target/mips/tcg/
H A Dtx79.decode3 # Copyright (C) 2021 Philippe Mathieu-Daudé
5 # SPDX-License-Identifier: LGPL-2.1-or-later
7 # Toshiba Appendix B C790-Specific Instruction Set Details
10 # Named attribute sets. These are used to make nice(er) names
/qemu/docs/system/i386/
H A Dtdx.rst5 Virtual Machine Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME)
12 -------------
29 device and it actually works as RAM. "-bios" option is chosen to load TDVF.
32 command line to specify and load TDVF is ``-bios OVMF.fd``
35 ---------------------
37 Unlike non-TDX VM, the CPU features (enumerated by CPU or MSR) of a TD are not
43 - Attributes:
44 - PKS (bit 30) controls whether Supervisor Protection Keys is exposed to TD,
46 - PERFMON (bit 63) controls whether PMU is exposed to TD.
48 - XSAVE related features (XFAM):
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/qemu/linux-headers/asm-powerpc/
H A Dkvm.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
100 * Contains EPCR, plus the upper half of 64-bit registers
101 * that are 32-bit on 32-bit implementations.
109 * IVORs are used -- contains IVOR0-15, plus additional IVORs
115 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG.
123 /* Enhanced debug -- DSRR0/1, SPRG9 */
126 /* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */
131 * External Proxy (EXP) -- EPR
135 /* External PID (E.PD) -- EPSC/EPLC */
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/qemu/tests/qtest/libqos/
H A Dqgraph_internal.h103 * otherwise: #-1
127 * otherwise: #-1
189 * e.g. a node has two "generic-sdhci", "emmc" and "sdcard"
217 * all machine-to-test paths.
248 * { "abstract" : true } attribute.
253 * qos_graph_node_set_availability(): sets the node identified
/qemu/system/
H A Dqemu-seccomp.c10 * the COPYING file in the top-level directory.
12 * Contributions after 2012-01-13 are licensed under the terms of the
18 #include "qemu/config-file.h"
50 * See 'NOTES' in 'man 2 clone' - s390 has 'flags' in
99 * Musl sets this in pthread_create too, but it is
275 return -1; in qemu_seccomp()
284 static int kill_process = -1; in qemu_seccomp_update_action()
285 if (kill_process == -1) { in qemu_seccomp_update_action()
305 int rc = -1; in seccomp_start()
322 error_setg_errno(errp, -rc, in seccomp_start()
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/qemu/docs/system/s390x/
H A Dvfio-ap.rst7 ------------
19 -------------------------
51 An AP queue is the means by which an AP command-request message is sent to an
57 which the AP command-request message is to be sent for processing.
63 * NQAP: to enqueue an AP command-request message to a queue
64 * DQAP: to dequeue an AP command-reply message from a queue
73 ----------------------------------------------
84 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
89 corresponds to an AP queue index (APQI) from 0-255. If a bit is set, the
94 changed by an AP command-request message sent to a usage domain from the
[all …]
/qemu/docs/tools/
H A Dqemu-img.rst6 --------
8 **qemu-img** [*standard options*] *command* [*command options*]
11 -----------
13 qemu-img allows you to create, convert and modify images offline. It can handle
16 **Warning:** Never use qemu-img to modify images in use by a running virtual
22 -------
24 .. program:: qemu-img
28 .. option:: -h, --help
32 .. option:: -V, --version
36 .. option:: -T, --trace [[enable=]PATTERN][,events=FILE][,file=FILE]
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/qemu/linux-headers/linux/
H A Dvfio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
37 /* Two-stage IOMMU */
43 * The No-IOMMU IOMMU offers no translation or isolation for devices and
44 * supports no ioctls outside of VFIO_CHECK_EXTENSION. Use of VFIO's No-IOMMU
100 /* -------- IOCTLs for VFIO file descriptor (/dev/vfio/vfio) -------- */
103 * VFIO_GET_API_VERSION - _IO(VFIO_TYPE, VFIO_BASE + 0)
114 * VFIO_CHECK_EXTENSION - _IOW(VFIO_TYPE, VFIO_BASE + 1, __u32)
123 * VFIO_SET_IOMMU - _IOW(VFIO_TYPE, VFIO_BASE + 2, __s32)
130 * Return: 0 on success, -errno on failure
135 /* -------- IOCTLs for GROUP file descriptors (/dev/vfio/$GROUP) -------- */
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/qemu/block/
H A Dfile-posix.c28 #include "qemu/error-report.h"
29 #include "block/block-io.h"
36 #include "block/thread-pool.h"
38 #include "block/raw-aio.h"
42 #include "scsi/pr-manager.h"
76 #include <linux/dm-ioctl.h>
146 * - DM_MPATH_PROBE_PATHS returns success, but before SG_IO completes, another
149 * - DM_MPATH_PROBE_PATHS failed all paths in the current path group, so we have
154 * failover), it's rare to have more than eight path groups - and even then
171 * s->fd. */
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/qemu/include/standard-headers/linux/
H A Dethtool.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
19 #include "standard-headers/linux/const.h"
20 #include "standard-headers/linux/types.h"
21 #include "standard-headers/linux/if_ether.h"
26 * have the same layout for 32-bit and 64-bit userland.
38 * struct ethtool_cmd - DEPRECATED, link control and status
43 * interface supports autonegotiation or auto-detection.
44 * Read-only.
48 * auto-detection.
56 * @autoneg: Enable/disable autonegotiation and auto-detection;
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/qemu/scripts/
H A Ddecodetree.py50 re_C_ident = '[a-zA-Z][a-zA-Z0-9_]*'
53 re_arg_ident = '&[a-zA-Z0-9_]*'
54 re_fld_ident = '%[a-zA-Z0-9_]*'
55 re_fmt_ident = '@[a-zA-Z0-9_]*'
56 re_pat_ident = '[a-zA-Z0-9_]*'
70 # (That is, if graph contains "A" -> ["B", "C"] then we must output
76 # element in the args attribute is a list of nodes which form a
85 # https://code.activestate.com/recipes/578272-topological-sort/
106 # This code wants the values in the dict to be specifically sets
112 - set(data.keys()))
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/qemu/include/hw/xen/interface/
H A Dmemory.h1 /* SPDX-License-Identifier: MIT */
28 * devices often have a 32-bit limitation even in 64-bit systems). If zero
36 #define XENMEMF_get_node(x) ((((x) >> 8) - 1) & 0xffu)
37 /* Flag to populate physmap with populate-on-demand entries */
84 * @out.extent_list provides GMFNs of the newly-allocated memory.
119 * command will be non-zero.
141 * specified domain (may be DOMID_SELF). Returns -ve errcode on failure.
149 * Returns -ve errcode on failure.
217 Stage-2 using the Normal Memory
218 Inner/Outer Write-Back Cacheable
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H A Dgrant_table.h1 /* SPDX-License-Identifier: MIT */
6 * page-ownership transfers.
31 * This capability-based system allows shared-memory communications
43 /* Some rough guidelines on accessing and updating grant-table entries
44 * in a concurrency-safe manner. For more information, Linux contains a
46 …* http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drivers/xen/grant-table.c;…
48 * NB. WMB is a no-op on current-generation x86 processors. However, a
52 * 1. Write ent->domid.
53 * 2. Write ent->frame:
55 * GTF_accept_transfer: Pseudo-phys frame slot being filled by new
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/qemu/target/i386/kvm/
H A Dxen-emu.c8 * See the COPYING file in the top-level directory.
14 #include "qemu/main-loop.h"
15 #include "qemu/error-report.h"
21 #include "system/address-spaces.h"
22 #include "xen-emu.h"
27 #include "hw/i386/apic-msidef.h"
44 #include "xen-compat.h"
64 *len = TARGET_PAGE_SIZE - (gva & ~TARGET_PAGE_MASK); in kvm_gva_to_gpa()
84 return -EFAULT; in kvm_gva_rw()
93 sz -= len; in kvm_gva_rw()
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H A Dtdx.c9 * SPDX-License-Identifier: GPL-2.0-or-later
13 #include "qemu/error-report.h"
15 #include "qemu/mmap-alloc.h"
27 #include "cpu-internal.h"
28 #include "host-cpu.h"
32 #include "hw/i386/tdvf-hob.h"
36 #include "standard-headers/asm-x86/kvm_para.h"
63 /* Valid after kvm_arch_init()->confidential_guest_kvm_init()->tdx_kvm_init() */
103 return -EINVAL; in tdx_ioctl_internal()
107 error_setg_errno(errp, -r, "TDX ioctl %s failed, hw_errors: 0x%llx", in tdx_ioctl_internal()
[all …]
/qemu/ui/
H A Dconsole-vc.c2 * SPDX-License-Identifier: MIT
14 #include "console-priv.h"
127 return c->chr ? c->chr->label : NULL; in qemu_text_console_get_label()
139 pixman_image_fill_rectangles(PIXMAN_OP_SRC, surface->image, in qemu_console_fill_rect()
151 surface->image, NULL, surface->image, in qemu_console_bitblt()
163 if (t_attrib->invers) { in vga_putcharxy()
164 bgcol = color_table_rgb[t_attrib->bold][t_attrib->fgcol]; in vga_putcharxy()
165 fgcol = color_table_rgb[t_attrib->bold][t_attrib->bgcol]; in vga_putcharxy()
167 fgcol = color_table_rgb[t_attrib->bold][t_attrib->fgcol]; in vga_putcharxy()
168 bgcol = color_table_rgb[t_attrib->bold][t_attrib->bgcol]; in vga_putcharxy()
[all …]
/qemu/
H A Dqemu-options.hx14 "-h or -help display this help and exit\n", QEMU_ARCH_ALL)
16 ``-h``
21 "-version display version information and exit\n", QEMU_ARCH_ALL)
23 ``-version``
28 "-machine [type=]name[,prop[=value][,...]]\n"
29 " selects emulated machine ('-machine help' for list)\n"
33 " dump-guest-core=on|off include guest memory in a core dump (default=on)\n"
34 " mem-merge=on|off controls memory merge support (default: on)\n"
35 " aes-key-wrap=on|off controls support for AES key wrapping (default=on)\n"
36 " dea-key-wrap=on|off controls support for DEA key wrapping (default=on)\n"
[all …]
/qemu/docs/devel/
H A Dmulti-process.rst1 Multi-process QEMU
6 This is the design document for multi-process QEMU. It does not
31 -------------
34 VM control point, where VMs can be created, migrated, re-configured, and
40 A multi-process QEMU
43 A multi-process QEMU involves separating QEMU services into separate
51 A QEMU control process would remain, but in multi-process mode, will
53 provide the user interface to hot-plug devices or live migrate the VM.
55 A first step in creating a multi-process QEMU is to separate IO services
62 ----------------------
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/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
10 Copyright (c) 1999-2016 Tensilica Inc.
44 /*----------------------------------------------------------------------
46 ----------------------------------------------------------------------*/
48 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
54 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
55 #define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
56 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
67 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
89 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
[all …]
/qemu/docs/system/
H A Dqemu-block-drivers.rst.inc5 any of the tools (like ``qemu-img``). This includes the preferred formats
10 ``qemu-img create`` and ``qemu-img convert`` using the ``-o`` option.
13 .. program:: image-formats
20 space. Use ``qemu-img info`` to know the real size used by the
21 image or ``ls -ls`` on Unix/Linux.
34 .. program:: image-formats
51 zero clusters, which allow efficient copy-on-read for sparse images.
69 use to unlock the LUKS key slot is given by the ``encrypt.key-secret``
73 If this is set to ``aes``, the image is encrypted with 128-bit AES-CBC.
74 The encryption key is given by the ``encrypt.key-secret`` parameter.
[all …]
/qemu/qapi/
H A Dmachine.json1 # -*- Mode: Python -*-
5 # See the COPYING file in the top-level directory.
12 { 'include': 'machine-common.json' }
18 # targets. Run "./configure --help" in the project root directory,
19 # and look for the \*-softmmu targets near the "--target-list" option.
30 # "qemu-system-" prefix to produce the corresponding QEMU
31 # executable name. This is true even for "qemu-system-x86_64".
52 'data': [ 'uninitialized', 'stopped', 'check-stop', 'operating', 'load' ] }
59 # @cpu-state: the virtual CPU's state
68 'data': { 'cpu-state': 'S390CpuState',
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/qemu/hw/arm/
H A Dmps2-tz.c17 * "mps2-an505" -- Cortex-M33 as documented in ARM Application Note AN505
18 * "mps2-an521" -- Dual Cortex-M33 as documented in Application Note AN521
19 * "mps2-an524" -- Dual Cortex-M33 as documented in Application Note AN524
20 * "mps2-an547" -- Single Cortex-M55 as documented in Application Note AN547
24 * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
37 * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide
40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines
43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
52 #include "qemu/error-report.h"
55 #include "hw/or-irq.h"
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