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/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h8 * In the Xtensa processor products released to date, all parameters
36 in all copies or substantial portions of the Software.
133 #define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */
164 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
170 * - must have all writable VPN and PPN fields;
230 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
231 …LB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
232 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all…
233 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
234 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 other…
[all …]
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_arith.c.inc263 TRANS(add_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
265 TRANS(sub_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
267 TRANS(and, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
268 TRANS(or, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
269 TRANS(xor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
270 TRANS(nor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl)
271 TRANS(andn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl)
272 TRANS(orn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
273 TRANS(slt, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
274 TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
[all …]
H A Dtrans_bit.c.inc181 TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl)
182 TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl)
183 TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
184 TRANS(clz_w, ALL, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)
185 TRANS(cto_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)
186 TRANS(ctz_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)
191 TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
197 TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
199 TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
201 TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
[all …]
H A Dtrans_branch.c.inc75 TRANS(beq, ALL, gen_rr_bc, TCG_COND_EQ)
76 TRANS(bne, ALL, gen_rr_bc, TCG_COND_NE)
77 TRANS(blt, ALL, gen_rr_bc, TCG_COND_LT)
78 TRANS(bge, ALL, gen_rr_bc, TCG_COND_GE)
79 TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)
80 TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU)
81 TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ)
82 TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE)
H A Dtrans_shift.c.inc75 TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
76 TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
77 TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
83 TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
85 TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
87 TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
/qemu/docs/system/arm/
H A Dcpu-features.rst16 As not all CPU types support all optional CPU features, then whether or
55 ``sve<N>`` CPU features. We also see that all the CPU features are
56 enabled, as they are all ``true``. (The ``sve<N>`` CPU features are all
58 all SVE vector lengths can be supported, when KVM is in use it's more
60 all.)
87 (4) Let's disable ``sve`` and see what happens to all the optional SVE
100 As expected they are now all ``false``.
114 when attempting to change all features at once an error could occur
116 all at once doesn't generate an error, because a feature's dependencies
119 attempt to make their desired changes all at once in order to ensure the
[all …]
/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h8 * In the Xtensa processor products released to date, all parameters
36 in all copies or substantial portions of the Software.
115 #define XCHAL_CA_ILLEGAL 15 /* no access allowed (all cause exceptions) mode */
148 * all its fields (VPN, PPN, ASID, CA) are all writable, and it
154 * - must have all writable VPN and PPN fields;
204 #define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
205 …PN_CONSTMASK 0x00000000 /* constant VPN bits, not including entry index bits; 0 if all writable */
206 #define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all…
207 #define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
208 #define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 other…
[all …]
/qemu/tests/qemu-iotests/
H A D293.out15 == all secrets should work ==
38 qemu-img: Can't add a keyslot - all keyslots are in use
40 == all secrets should work again ==
50 == erase all keys of secret 2==
51 == erase all keys of secret 1==
52 == erase all keys of secret 0==
54 qemu-img: All the active keyslots match the (old) password that was given and erasing them will era…
86 qemu-img: Attempt to erase the only active keyslot 0 which will erase all the data in the image irr…
87 qemu-img: All the active keyslots match the (old) password that was given and erasing them will era…
H A D06066 OPEN_RW="open -o overlap-check=all $TEST_IMG"
122 _check_test_img -r all
145 _check_test_img -r all
268 _check_test_img -r all
281 _check_test_img -r all
290 _check_test_img -r all
302 _check_test_img -r all
311 _check_test_img -r all
338 _check_test_img -r all
355 _check_test_img -r all
[all …]
H A D267.out3 === No block devices at all ===
35 List of snapshots present on all disks:
46 List of snapshots present on all disks:
71 List of snapshots present on all disks:
96 List of snapshots present on all disks:
107 List of snapshots present on all disks:
121 List of snapshots present on all disks:
136 List of snapshots present on all disks:
147 List of snapshots present on all disks:
168 List of snapshots present on all disks:
/qemu/docs/tools/
H A Dqemu-trace-stap.rst36 List all the probe names provided by *BINARY* that match
46 any of the listed names. If no *PATTERN* is given, the all possible
49 For example, to list all probes available in the |qemu_system|
74 Multiple *PATTERN* arguments may be given, causing all matching probes
76 capable of tracing all known QEMU probes concurrently without overflowing
80 invocation of the QEMU process(es). It will match probes on all
81 existing running processes and all future launched processes,
93 For example, to monitor all processes executing |qemu_system|
94 as found on ``$PATH``, displaying all I/O related probes:
/qemu/trace/
H A Dmeson.build60 trace_events_all = custom_target('trace-events-all',
61 output: 'trace-events-all',
69 trace_ust_all_h = custom_target('trace-ust-all.h',
70 output: 'trace-ust-all.h',
72 … command: [ tracetool, '--group=all', '--format=ust-events-h', '@INPUT@', '@OUTPUT@' ],
74 trace_ust_all_c = custom_target('trace-ust-all.c',
75 output: 'trace-ust-all.c',
77 … command: [ tracetool, '--group=all', '--format=ust-events-c', '@INPUT@', '@OUTPUT@' ],
/qemu/docs/
H A Drdma.txt63 is in active use, then enabling this feature will cause all 8GB to
69 $ migrate_set_capability rdma-pin-all on # disabled by default
71 Performing this action will cause all 8GB to be pinned, so if that's
79 Note: for very large virtual machines (hundreds of GBs), pinning all
80 *all* of the memory of your virtual machine in the kernel is very expensive
119 For example, in the same 8GB RAM example with all 8GB of memory in
123 1. rdma-pin-all disabled total time: approximately 7.5 seconds @ 9.5 Gbps
124 2. rdma-pin-all enabled total time: approximately 4 seconds @ 26 Gbps
130 migration *downtime*. This is because, without this feature, all of the
163 basically done. All that is required is for the sender
[all …]
H A Dimage-fuzzer.txt35 images, indicates their results and collects all test related artifacts (logs,
37 The test means execution of all available commands under test with the same
71 the '--command' argument. Each command is a list containing a SUT and all its
107 'fuzz.py' contains all fuzzing functions, one per image field. It's assumed
111 of bits are set to ones. All fuzzed values are checked on non-equality to the
177 3. Image template should describe a general structure invariant for all
197 of all possible test commands can be available in the test runner
201 16. All files related to a test result should be collected: a test image,
221 allows the fuzzer to generate the pool of all available areas can be fuzzed
234 Action pool is all available elements of an image structure that generated
/qemu/
H A DMakefile33 all: target
34 .PHONY: all clean distclean recurse-all dist msi FORCE
41 # All following code might depend on configuration variables
103 $(NINJA) -t targets all | sed 's/:.*//; $$!s/$$/ \\/'; \
130 all update-buildoptions: $(SRC_PATH)/scripts/meson-buildoptions.sh target
153 ninja-cmd-goals = $(or $(MAKECMDGOALS), all)
157 # "ninja -t targets" also lists all prerequisites. If build system
183 all: recurse-all target
185 SUBDIR_RULES=$(foreach t, all clean distclean, $(addsuffix /$(t), $(SUBDIRS)))
190 .PHONY: recurse-all recurse-clean
[all …]
/qemu/include/exec/
H A Dcputlb.h45 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
103 * Flush one page from the TLB of the specified CPU, for all
113 * Flush one page from the TLB of all CPUs, for all
136 * Flush the entire TLB for all CPUs, for all MMU indexes.
161 * Flush one page from the TLB of all CPUs, for the specified
176 * Flush all entries from the TLB of the specified CPU, for the specified
186 * Flush all entries from the TLB of all CPUs, for the specified
219 * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
/qemu/docs/devel/
H A Dmulti-thread-tcg.rst29 user-space thread. This is enabled by default for all FE/BE
42 inter-vCPU dependencies and all vCPUs should be able to run at full
82 translation buffer which contains code running on all cores. Any
89 DESIGN REQUIREMENT: Add locking around all code generation and TB
106 which when full will force a flush of all translations and start from
115 This is done with the async_safe_run_on_cpu() mechanism to ensure all
142 linked list of all Translation Blocks in that page (see page_next).
196 - TLB Flush All/Page
212 restarts all flush operations have completed.
214 TLB flag updates are all done atomically and are also protected by the
[all …]
H A Dreset.rst21 to control it. All resettable control functions must be called while holding
41 with ``SHUTDOWN_CAUSE_SNAPSHOT_LOAD``.) Almost all devices should treat
103 For example, consider a SCSI controller. Resetting the controller puts all
119 startup), all first phases of all objects are executed, then all second phases
120 and then all third phases.
146 DMA capable devices are expected to cancel all outstanding DMA operations
165 ``phases.exit()``. They all take the object as parameter. The *enter* method
230 In the above example, we override all three phases. It is possible to override
290 every reset child of the given resettable object. All children must be
349 the three-phase mechanism listed above. It resets all objects
[all …]
H A Dtracing.rst45 "trace-events" file. All directories which contain "trace-events" files must be
50 The individual "trace-events" files are merged into a "trace-events-all" file,
83 all events be declared directly in the sub-directory that uses them. The only
127 cannot include all user-defined struct declarations and it is therefore
219 If multiple backends are enabled, the trace is sent to them all.
267 simpletrace.py script. The script takes the "trace-events-all" file and the
270 ./scripts/simpletrace.py trace-events-all trace-12345
272 You must ensure that the same "trace-events-all" file was used to build QEMU,
299 them). All events are logged at LOG_INFO level.
318 While running an instrumented QEMU, LTTng should be able to list all available
[all …]
H A Dtcg-plugins.rst24 All plugins need to declare a symbol which exports the plugin API
62 callbacks to some or all instructions when they are executed.
66 callback conditionally, with condition being evaluated inline. All those inline
73 Finally when QEMU exits all the registered *atexit* callbacks are
91 All code will go through a translation phase although not all
101 Not all instructions in a block will always execute so if its
163 has executed while all vCPUs are quiescent.
H A Dcode-of-conduct.rst7 volunteers from all over the world. Diversity is one of our strengths,
17 * Be respectful. Not all of us will agree all the time. Disagreements, both
18 social and technical, happen all the time and the QEMU community is no
43 This code of conduct applies to all spaces managed by the QEMU project.
/qemu/include/io/
H A Dchannel.h99 * This class defines the contract that all subclasses
222 * It is not required for all @iov to be filled with
270 * It is not required for all @iov data to be fully
278 * All file descriptors will be sent if at least one
310 * The function will wait for all requested data
316 * before all requested data has been read, an error
319 * Returns: 1 if all bytes were read, 0 if end-of-file
340 * The function will wait for all requested data
344 * If end-of-file occurs before all requested data
347 * Returns: 0 if all bytes were read, or -1 on error
[all …]
/qemu/tests/functional/acpi-bits/bits-config/
H A Dbits-cfg.txt5 # following keywords; BITS will then run all of the requested operations, then
9 # acpi: Dump all ACPI structures.
10 # smbios: Dump all SMBIOS structures.
15 # Uncomment the following to run all available batch operations
/qemu/docs/system/
H A Dcpu-models-x86.rst.inc72 across all desired hosts.
126 all, of the named CPU models listed above. In general all of these
153 Must be explicitly turned on for all Intel CPU models.
163 Must be explicitly turned on for all Intel CPU models.
173 Should be explicitly turned on for all Intel CPU models.
175 Note that not all CPU hardware will support this feature.
183 Must be explicitly turned on for all Intel CPU models.
277 across all desired hosts.
304 all, of the named CPU models listed above. In general all of these
321 Must be explicitly turned on for all AMD CPU models.
[all …]
/qemu/contrib/ivshmem-client/
H A Dmain.c72 "int <peer> all: notify all vectors of a peer\n" in ivshmem_client_cmdline_help()
73 "int all: notify all vectors of all peers (excepting us)\n"); in ivshmem_client_cmdline_help()
104 } else if (!strcmp(token, "int all")) { in ivshmem_client_handle_stdin_command()
113 } else if (sscanf(token, "int %d all", &peer_id) == 1) { in ivshmem_client_handle_stdin_command()
233 /* disconnected from server, reset all peers */ in main()

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