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/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
46 * base address: 0x000003a0
50 /* register address for bitfield rx dma good octet counter lsw [1f:0] */
52 /* register address for bitfield rx dma good packet counter lsw [1f:0] */
54 /* register address for bitfield tx dma good octet counter lsw [1f:0] */
56 /* register address for bitfield tx dma good packet counter lsw [1f:0] */
59 /* register address for bitfield rx dma good octet counter msw [3f:20] */
61 /* register address for bitfield rx dma good packet counter msw [3f:20] */
[all …]
/linux-5.10/Documentation/devicetree/bindings/mtd/
Dmtd-physmap.txt1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
13 device width times the number of interleaved chips.
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
Dorion-nand.txt4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
16 address space. See partition.txt for more detail.
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/net/
Dgpmc-eth.txt4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
/linux-5.10/Documentation/devicetree/bindings/bus/
Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19 addresses in the GMI address space. Should be 2.
[all …]
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
32 /* register address for bitfield rpf_new_rpf_en */
40 /* width of bitfield rpf_new_rpf_en */
51 /* register address for bitfield l2_uc_req_tag0{f}[2:0] */
59 /* width of bitfield l2_uc_req_tag0{f}[2:0] */
69 /* register address for bitfield rpf_l2_bc_req_tag */
77 /* width of bitfield rpf_l2_bc_req_tag */
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
94 /* width of bitfield rpf_rss_red1_data[4:0] */
105 /* register address for bitfield vlan_req_tag0{f}[3:0] */
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 mmc-hs200-1_8v;
19 #address-cells = <2>;
20 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <1>;
28 compatible = "cfi-flash";
30 bank-width = <2>;
31 device-width = <1>;
35 compatible = "fsl,ifc-nand";
[all …]
Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
/linux-5.10/drivers/acpi/acpica/
Dhwvalid.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwvalid - I/O request validation
6 * Copyright (C) 2000 - 2020, Intel Corp.
18 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width);
22 * conditionally illegal. This table must remain ordered by port address.
27 * later (meaning that the BIOS itelf is post-XP.)
37 * RTC: Real-time clock
77 * PARAMETERS: Address Address of I/O port/register
82 * DESCRIPTION: Validates an I/O request (address/length). Certain ports are
90 acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) in acpi_hw_validate_io_request() argument
[all …]
Dexregion.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: exregion - ACPI default op_region (address space) handlers
6 * Copyright (C) 2000 - 2020, Intel Corp.
21 * PARAMETERS: function - Read or Write operation
22 * address - Where in the space to read or write
23 * bit_width - Field width in bits (8, 16, or 32)
24 * value - Pointer to in or out value
25 * handler_context - Pointer to Handler's context
26 * region_context - Pointer to context specific to the
31 * DESCRIPTION: Handler for the System Memory address space (Op Region)
[all …]
/linux-5.10/arch/arm64/boot/dts/realtek/
Drtd129x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/reset/realtek,rtd1295.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
20 reserved-memory {
21 #address-cells = <1>;
22 #size-cells = <1>;
[all …]
Drtd139x.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/realtek,rtd1295.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
34 no-map;
[all …]
Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
/linux-5.10/drivers/video/console/
Dsticore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/video/console/sticore.c -
7 * Copyright (C) 2001-2020 Helge Deller <deller@gmx.de>
8 * Copyright (C) 2001-2002 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
11 * - call STI in virtual mode rather than in real mode
12 * - screen blanking with state_mgmt() in text mode STI ?
13 * - try to make it work on m68k hp workstations ;)
29 #include <asm/parisc-device.h>
46 * 0 - Black
47 * 1 - White
[all …]
/linux-5.10/Documentation/devicetree/bindings/misc/
Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
23 compatible = "ifm,o2d-csi";
[all …]
/linux-5.10/include/video/
Ds1d13xxxfb.h4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
44 #define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
47 #define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
50 #define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
52 #define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
55 #define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
Ddc_debug.c43 if (dc->debug.surface_trace) \
48 if (dc->debug.timing_trace) \
53 if (dc->debug.clock_trace) \
63 DC_LOGGER_INIT(dc->ctx->logger); in pre_surface_trace()
71 "plane_state->visible = %d;\n" in pre_surface_trace()
72 "plane_state->flip_immediate = %d;\n" in pre_surface_trace()
73 "plane_state->address.type = %d;\n" in pre_surface_trace()
74 "plane_state->address.grph.addr.quad_part = 0x%llX;\n" in pre_surface_trace()
75 "plane_state->address.grph.meta_addr.quad_part = 0x%llX;\n" in pre_surface_trace()
76 "plane_state->scaling_quality.h_taps = %d;\n" in pre_surface_trace()
[all …]
/linux-5.10/arch/arm/boot/dts/
Drtd1195.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
3 * Copyright (c) 2017-2019 Andreas Färber
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/realtek,rtd1195.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a7";
[all …]
/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
[all …]
/linux-5.10/drivers/staging/sm750fb/
Dsm750_accel.c1 // SPDX-License-Identifier: GPL-2.0
23 writel(regValue, accel->dprBase + offset); in write_dpr()
28 return readl(accel->dprBase + offset); in read_dpr()
33 writel(data, accel->dpPortBase); in write_dpPort()
90 u32 x, u32 y, u32 width, u32 height, in sm750_hw_fillrect() argument
95 if (accel->de_wait() != 0) { in sm750_hw_fillrect()
101 return -1; in sm750_hw_fillrect()
122 ((width << DE_DIMENSION_X_SHIFT) & DE_DIMENSION_X_MASK) | in sm750_hw_fillrect()
135 * @sBase: Address of source: offset in frame buffer
139 * @dBase: Address of destination: offset in frame buffer
[all …]
/linux-5.10/drivers/dma/
Dfsldma.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
129 /* Define macros for fsldma_chan->feature property */
[all …]
/linux-5.10/arch/mips/boot/dts/netlogic/
Dxlp_evp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-EVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
24 reg-shift = <2>;
25 reg-io-width = <4>;
[all …]
Dxlp_fvp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-FVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
24 reg-shift = <2>;
25 reg-io-width = <4>;
[all …]
Dxlp_svp.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 model = "netlogic,XLP-SVP";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <1>;
16 compatible = "simple-bus";
24 reg-shift = <2>;
25 reg-io-width = <4>;
[all …]
/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
[all …]

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