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/linux-6.8/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
Dmmu.json3 "PublicDescription": "Duration of a translation table walk handled by the MMU",
6 "BriefDescription": "Duration of a translation table walk handled by the MMU"
9 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
12 …": "Duration of a Stage 1 translation table walk handled by the MMU. This event is not counted whe…
15 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
18 …": "Duration of a Stage 2 translation table walk handled by the MMU. This event is not counted whe…
21 "PublicDescription": "Duration of a translation table walk requested by the LSU",
24 "BriefDescription": "Duration of a translation table walk requested by the LSU"
27 … "PublicDescription": "Duration of a translation table walk requested by the instruction side",
30 "BriefDescription": "Duration of a translation table walk requested by the instruction side"
[all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/snowridgex/
Dvirtual-memory.json20 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
28 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
36 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
44 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
52 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
74 …e number of page walks completed due to stores whose address translations missed in all Translatio…
82 …e number of page walks completed due to stores whose address translations missed in all Translatio…
90 …e number of page walks completed due to stores whose address translations missed in all Translatio…
98 …e number of page walks completed due to stores whose address translations missed in all Translatio…
106 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/elkhartlake/
Dvirtual-memory.json20 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
28 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
36 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
44 …mpleted due to loads (including SW prefetches) whose address translations missed in all Translatio…
52 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
74 …e number of page walks completed due to stores whose address translations missed in all Translatio…
82 …e number of page walks completed due to stores whose address translations missed in all Translatio…
90 …e number of page walks completed due to stores whose address translations missed in all Translatio…
98 …e number of page walks completed due to stores whose address translations missed in all Translatio…
106 …g from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals.",
[all …]
/linux-6.8/drivers/of/
Dfdt_address.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FDT Address translation based on u-boot fdt_support.c which in turn was
4 * based on the kernel unflattened DT address translation code.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
20 /* Max address size we deal with */
30 while(na--) in of_dump_addr()
54 prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); in fdt_bus_default_count_cells()
62 prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); in fdt_bus_default_count_cells()
84 return da - cp; in fdt_bus_default_map()
93 addr[na - 2] = cpu_to_fdt32(a >> 32); in fdt_bus_default_translate()
[all …]
/linux-6.8/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
15 controller registers provide the control for the translation from the offset
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
[all …]
/linux-6.8/Documentation/devicetree/bindings/iommu/
Diommu.txt10 * Remap address space to allow devices to access physical memory ranges that
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
20 address regions.
22 * Provide address space isolation between multiple contexts.
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
[all …]
/linux-6.8/arch/arm64/mm/
Dfault.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 1995-2004 Russell King
21 #include <linux/page-flags.h>
36 #include <asm/debug-monitors.h>
115 esr_to_fault_info(esr)->name); in mem_abort_decode()
125 return __pa_symbol(mm->pgd); in mm_to_pgd_phys()
127 return (unsigned long)virt_to_phys(mm->pgd); in mm_to_pgd_phys()
141 mm = current->active_mm; in show_pte()
143 pr_alert("[%016lx] user address but active_mm is swapper\n", in show_pte()
151 pr_alert("[%016lx] address between user and kernel address ranges\n", in show_pte()
[all …]
/linux-6.8/Documentation/scsi/
Daha152x.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec AHA-1520/1522 SCSI driver for Linux (aha152x)
8 Copyright |copy| 1993-1999 Jürgen Fischer <fischer@norbit.de>
14 bottom-half handler complete()).
26 IOPORT base io address (0x340/0x140)
27 IRQ interrupt level (9-12; default 11)
28 SCSI_ID scsi id of controller (0-7; default 7)
33 EXT_TRANS: enable extended translation (0/1: default 0 [off])
42 - DAUTOCONF
43 use configuration the controller reports (AHA-152x only)
[all …]
/linux-6.8/Documentation/virt/kvm/x86/
Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
31 - dirty tracking:
33 and framebuffer-based displays
34 - footprint:
[all …]
/linux-6.8/Documentation/arch/arm64/
Dtagged-pointers.rst10 addresses in the AArch64 translation system and their potential uses
13 The kernel configures the translation tables so that translations made
15 the virtual address ignored by the translation hardware. This frees up
20 --------------------------------------
23 an address tag of 0x00, unless the application enables the AArch64
24 Tagged Address ABI explicitly
25 (Documentation/arch/arm64/tagged-address-abi.rst).
29 - pointer arguments to system calls, including pointers in structures
32 - the stack pointer (sp), e.g. when interpreting it to deliver a
35 - the frame pointer (x29) and frame records, e.g. when interpreting
[all …]
Dmemory.rst8 Linux kernel. The architecture allows up to 4 levels of translation
11 AArch64 Linux uses either 3 levels or 4 levels of translation tables
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
15 virtual address, are used but the memory layout is the same.
17 ARMv8.2 adds optional support for Large Virtual Address space. This is
19 number of descriptors in the first level of translation.
23 virtual address. The swapper_pg_dir contains only kernel (global)
24 mappings while the user pgd contains only user (non-global) mappings.
25 The swapper_pg_dir address is written to TTBR1 and never written to
[all …]
/linux-6.8/drivers/acpi/acpica/
Drsdumpinfo.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: rsdumpinfo - Tables used to display resource descriptors.
59 "Start-Dependent-Functions", NULL},
70 "End-Dependent-Functions", NULL}
75 {ACPI_RSD_1BITFLAG, ACPI_RSD_OFFSET(io.io_decode), "Address Decoding",
77 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.minimum), "Address Minimum", NULL},
78 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(io.maximum), "Address Maximum", NULL},
80 {ACPI_RSD_UINT8, ACPI_RSD_OFFSET(io.address_length), "Address Length",
87 {ACPI_RSD_UINT16, ACPI_RSD_OFFSET(fixed_io.address), "Address", NULL},
89 "Address Length", NULL}
[all …]
Drsaddr.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: rsaddr - Address resource descriptors (16/32/64)
17 * acpi_rs_convert_address16 - All WORD (16-bit) address resources
29 /* Resource Type, General Flags, and Type-Specific Flags */
35 * Address Granularity
36 * Address Range Minimum
37 * Address Range Maximum
38 * Address Translation Offset
39 * Address Length
41 {ACPI_RSC_MOVE16, ACPI_RS_OFFSET(data.address16.address.granularity),
[all …]
/linux-6.8/Documentation/devicetree/bindings/powerpc/fsl/
Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
17 between child address space and parent address space
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cells = <1>;
30 There must be a sub-node for each job queue present in RAID Engine
31 This node must be a sub-node of the main RAID Engine node
[all …]
/linux-6.8/Documentation/driver-api/
Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
8 registers and memory translation windows, as well as non common features like
9 scratchpad and message registers. Scratchpad registers are read-and-writable
11 exchange a small amount of information at a fixed address. Message registers can
36 ----------------------------------------
42 inbound translation configured on the local ntb port and outbound translation
46 Inbound translation:
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
[all …]
/linux-6.8/drivers/dma/fsl-dpaa2-qdma/
Ddpaa2-qdma.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 u32 rbpcmd; /* Route-by-port command */
37 #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
38 #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
53 #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */
54 #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */
55 /* Flow Context: 49bit physical address */
57 #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */
62 #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
63 #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
[all …]
/linux-6.8/arch/arm64/kvm/
Dstacktrace.c1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * 1) Non-protected nVHE mode - the host can directly access the
12 * 2) pKVM (protected nVHE) mode - the host cannot directly access
28 unsigned long low = (unsigned long)stacktrace_info->overflow_stack_base; in stackinfo_get_overflow()
52 unsigned long low = (unsigned long)stacktrace_info->stack_base; in stackinfo_get_hyp()
73 * kvm_nvhe_stack_kern_va - Convert KVM nVHE HYP stack addresses to a kernel VAs
76 * allow for guard pages below the stack. Consequently, the fixed offset address
77 * translation macros won't work here.
102 *addr = *addr - stack_hyp.low + stack_kern.low; in kvm_nvhe_stack_kern_va()
107 * Convert a KVN nVHE HYP frame record address to a kernel VA
[all …]
/linux-6.8/Documentation/admin-guide/mm/
Dconcepts.rst7 systems from MMU-less microcontrollers to supercomputers. The memory
12 address to a physical address.
23 address ranges. Besides, different CPU architectures, and even
25 of how these address ranges are defined.
36 address. When the CPU decodes an instruction that reads (or
38 address encoded in that instruction to a `physical` address that the
49 translation from a virtual address used by programs to the physical
50 memory address. The page tables are organized hierarchically.
56 register. When the CPU performs the address translation, it uses this
58 virtual address are used to index an entry in the top level page
[all …]
/linux-6.8/Documentation/devicetree/bindings/arm/
Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
23 The CoreSight Address Translation Unit (CATU) translates addresses between an
[all …]
/linux-6.8/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
12 …"PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includ…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 … level 2 cache by cache maintenance operations that operate by a virtual address, or by external c…
/linux-6.8/include/uapi/linux/
Diommu.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
38 * An external abort occurred fetching (or updating) a translation
44 * Could not access the page table entry (Bad address),
45 * actual translation fault
55 /* Output address of a translation stage caused Address Size fault */
60 * struct iommu_fault_unrecoverable - Unrecoverable fault data
63 * @pasid: Process Address Space ID
66 * @addr: offending page address
67 * @fetch_addr: address that caused a fetch abort, if any
82 * struct iommu_fault_page_request - Page Request data
[all …]
/linux-6.8/tools/perf/pmu-events/arch/x86/goldmontplus/
Dvirtual-memory.json6 …walks completed due to demand data loads (including SW prefetches) whose address translations miss…
14 …walks completed due to demand data loads (including SW prefetches) whose address translations miss…
22 …walks completed due to demand data loads (including SW prefetches) whose address translations miss…
38 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat…
46 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat…
54 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat…
70 … (EPT), and does not count during the rest of the translation. The EPT is used for translating Gu…
78 …d a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an …
86 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
94 …"PublicDescription": "Counts page walks completed due to instruction fetches whose address transla…
[all …]
/linux-6.8/Documentation/arch/x86/
Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
17 PCIe Address Translation Services (ATS) along with Page Request Interface
19 application page-faults. For more information please refer to the PCIe
26 sync. When an ATS lookup fails for a virtual address, the device should
27 use the PRI in order to request the virtual address to be paged into the
29 translation before use.
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
39 executed in the hardware by SWQ interface, SIOV uses Process Address Space
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
[all …]
/linux-6.8/net/batman-adv/
Dsend.h1 /* SPDX-License-Identifier: GPL-2.0 */
70 * batadv_send_skb_via_tt() - send an skb via TT lookup
74 * @vid: the vid to be used to search the translation table
76 * Look up the recipient node for the destination address in the ethernet
77 * header via the translation table. Wrap the given skb into a batman-adv
91 * batadv_send_skb_via_tt_4addr() - send an skb via TT lookup
96 * @vid: the vid to be used to search the translation table
98 * Look up the recipient node for the destination address in the ethernet
99 * header via the translation table. Wrap the given skb into a batman-adv
100 * unicast-4addr header. Then send this frame to the according destination
/linux-6.8/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
Dl2_cache.json4 …ruction accesses. Accesses are for misses in the first level caches or translation resolutions due…
8 …instruction accesses. Accesses are for misses in the level 1 caches or translation resolutions due…
12 …"PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includ…
20 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
24 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
28 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
32 …instruction accesses, accesses are for misses in the level 1 caches or translation resolutions due…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 … level 2 cache by cache maintenance operations that operate by a virtual address, or by external c…

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