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/qemu/hw/ppc/
H A Dppc.c4 * Copyright (c) 2003-2007 Jocelyn Mayer
30 #include "exec/cpu-interrupt.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/error-report.h"
47 CPUPPCState *env = &cpu->env; in ppc_set_irq()
53 old_pending = env->pending_interrupts; in ppc_set_irq()
56 env->pending_interrupts |= irq; in ppc_set_irq()
58 env->pending_interrupts &= ~irq; in ppc_set_irq()
61 if (old_pending != env->pending_interrupts) { in ppc_set_irq()
68 trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, in ppc_set_irq()
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/qemu/hw/misc/
H A Dled.c4 * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "hw/qdev-properties.h"
43 trace_led_set_intensity(s->description, s->color, intensity_percent); in led_set_intensity()
44 if (intensity_percent != s->intensity_percent) { in led_set_intensity()
45 trace_led_change_intensity(s->description, s->color, in led_set_intensity()
46 s->intensity_percent, intensity_percent); in led_set_intensity()
48 s->intensity_percent = intensity_percent; in led_set_intensity()
53 return s->intensity_percent; in led_get_intensity()
66 led_set_state(s, !!new_state == s->gpio_active_high); in led_set_state_gpio_handler()
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/qemu/docs/
H A Dblock-replication.txt2 ----------------------------------------
8 See the COPYING file in the top-level directory.
11 for COLO (COarse-grain LOck-stepping) where the Secondary VM is running.
12 It can also be applied for FT/HA (Fault-tolerance/High Assurance) scenario,
18 High availability solutions such as micro checkpoint and COLO will do
30 +----------------------+ +------------------------+
32 +----------------------+ +------------------------+
36 | /-------------\
38 |---------(1)----------+ | Disk Buffer |
40 | (3) \-------------/
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H A Dxbzrle.txt5 of VM downtime and the total live-migration time of Virtual machines.
19 A small cache size will result in high cache miss rate.
55 XBZRLE has a sustained bandwidth of 2-2.5 GB/s for typical workloads making it
56 ideal for in-line, real-time encoding such as is needed for live-migration.
91 3. Set the XBZRLE cache size - the cache size is in MBytes and should be a
93 {qemu} migrate_set_parameter xbzrle-cache-size 256m
96 {qemu} migrate -d tcp:destination.host:4444
99 Migration status: active
115 xbzrle cache miss: the number of cache misses to date - high cache-miss rate
H A DCOLO-FT.txt1 COarse-grained LOck-stepping Virtual Machines for Non-stop Service
2 ----------------------------------------
8 See the COPYING file in the top-level directory.
14 application-agnostic software-implemented hardware fault tolerance,
15 also known as "non-stop service".
17 COLO (COarse-grained LOck-stepping) is a high availability solution.
45 +------------+ +-----------------------+ +------------------------+ +------------+
46 | | | HeartBeat +<----->+ HeartBeat | | |
47 | Primary VM | +-----------+-----------+ +-----------+------------+ |Secondary VM|
49 | | +-----------|-----------+ +-----------|------------+ | |
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/qemu/rust/qemu-api/src/
H A Dirq.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
29 /// As far as devices are concerned, interrupt sources are always active-high:
65 /// Send a high-low pulse to the interrupt sink.
71 /// Send a high (`true`) value to the interrupt sink.
91 pub(crate) const fn as_ptr(&self) -> *mut *mut bindings::IRQState { in as_ptr()
95 pub(crate) const fn slice_as_ptr(slice: &[Self]) -> *mut *mut bindings::IRQState { in slice_as_ptr()
102 fn default() -> Self { in default()
/qemu/include/qemu/
H A Dtimer.h6 #include "qemu/host-utils.h"
187 * in nanoseconds, or -1 if no timer is set to expire.
189 * Returns: time until expiry in nanoseconds or -1
276 * Frees a timer_list. It must have no active timers.
284 * Determine whether a timer list has active timers
312 * expires. Return -1 if there are no timers.
315 * timer expires -1 if none
386 * Returns: the deadline in nanoseconds or -1 if no
507 * with an AioContext---each of them runs its timer callbacks in its own
607 * @ts: the timer to be de-initialised
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/qemu/include/hw/ssi/
H A Dssi.h4 * In principle SSI is a point-point interface. As such the qemu
16 #include "hw/qdev-core.h"
21 #define TYPE_SSI_PERIPHERAL "ssi-peripheral"
25 #define SSI_GPIO_CS "ssi-gpio-cs"
40 * This is called when the device cs is active (true by default).
48 /* define whether or not CS exists and is active low/high */
51 /* if you have non-standard CS behaviour override this to take control
103 * via the child<> property, and so the reference-count-drop done here
/qemu/include/hw/misc/
H A Dled.h4 * Copyright (C) 2020 Philippe Mathieu-Daudé <f4bug@amsat.org>
6 * SPDX-License-Identifier: GPL-2.0-or-later
12 #include "hw/qdev-core.h"
23 * https://www.lumileds.com/products/color-leds/luxeon-rebel-color/
48 * Determines whether a GPIO is using a positive (active-high)
/qemu/tests/qemu-iotests/
H A D1514 # Tests for active mirroring
38 qemu_img('create', '-f', iotests.imgfmt, source_img, '128M')
39 qemu_img('create', '-f', iotests.imgfmt, target_img, '128M')
43 'node-name': 'source-node',
49 blk_target = {'node-name': 'target-node',
57 self.vm.add_device('virtio-blk,id=vblk,drive=source')
73 'write -P 1 0 %i' % self.image_len);
77 self.vm.hmp_qemu_io('source', 'aio_write -P 2 %i 1M' % offset)
79 self.vm.hmp_qemu_io('source', 'aio_write -z %i 1M' % offset)
82 self.vm.cmd('blockdev-mirror',
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/qemu/include/hw/xen/interface/hvm/
H A Dparams.h1 /* SPDX-License-Identifier: MIT */
34 * How should CPU0 event-channel notifications be delivered?
36 * If val == 0 then CPU0 event-channel notifications are not delivered.
62 * val[15:8] is interrupt flag of the PPI used by event-channel:
64 * bit 9: the PPI is active low(1) or high(0)
65 * val[7:0] is a PPI number used by event-channel.
74 * These are not used by Xen. They are here for convenience of HVM-guest
89 …* (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hyperviso…
99 * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
100 * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
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/qemu/hw/usb/
H A Dhcd-ehci-sysbus.c19 #include "hw/qdev-properties.h"
20 #include "hw/usb/hcd-ehci.h"
24 .name = "ehci-sysbus",
35 DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
43 EHCIState *s = &i->ehci; in usb_ehci_sysbus_realize()
46 sysbus_init_irq(d, &s->irq); in usb_ehci_sysbus_realize()
53 EHCIState *s = &i->ehci; in usb_ehci_sysbus_reset()
63 EHCIState *s = &i->ehci; in ehci_sysbus_init()
65 s->capsbase = sec->capsbase; in ehci_sysbus_init()
66 s->opregbase = sec->opregbase; in ehci_sysbus_init()
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H A Ddev-uas.c9 * See the COPYING file in the top-level directory.
14 #include "qemu/config-file.h"
16 #include "qemu/error-report.h"
17 #include "qemu/main-loop.h"
24 #include "hw/qdev-properties.h"
29 /* --------------------------------------------------------------------- */
107 /* --------------------------------------------------------------------- */
136 #define TYPE_USB_UAS "usb-uas"
147 bool active; member
163 /* --------------------------------------------------------------------- */
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/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/qemu/hw/i2c/
H A Dsmbus_eeprom.c31 #include "hw/qdev-properties.h"
38 #define TYPE_SMBUS_EEPROM "smbus-eeprom"
55 uint8_t *data = eeprom->data; in eeprom_receive_byte()
56 uint8_t val = data[eeprom->offset++]; in eeprom_receive_byte()
58 eeprom->accessed = true; in eeprom_receive_byte()
61 dev->i2c.address, val); in eeprom_receive_byte()
69 uint8_t *data = eeprom->data; in eeprom_write_data()
71 eeprom->accessed = true; in eeprom_write_data()
74 dev->i2c.address, buf[0], buf[1]); in eeprom_write_data()
77 eeprom->offset = buf[0]; in eeprom_write_data()
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/qemu/include/hw/
H A Dqdev-core.h22 * -----------
31 * information to the caller and must be re-entrant.
57 * ---------------
62 * DeviceListener can save the QOpts passed to it for re-using it
73 DEV_NVECTORS_UNSPECIFIED = -1,
101 * struct DeviceClass - The base class for all devices.
107 * @sync_config: Callback function invoked when QMP command device-sync-config
136 * ensures a compile-time error if someone attempts to assign
137 * dc->props directly.
148 * @user_creatable: Can user instantiate with -device / device_add?
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/qemu/hw/intc/
H A Darmv7m_nvic.c4 * Copyright (c) 2006-2007 CodeSourcery.
20 #include "hw/qdev-properties.h"
24 #include "target/arm/cpu-features.h"
33 * the num-irq property counts the number of external IRQ lines
44 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
56 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
58 /* Effective running priority of the CPU when no exception is active
62 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
71 if (qemu_irq_is_connected(s->sysresetreq)) { in signal_sysresetreq()
72 qemu_irq_pulse(s->sysresetreq); in signal_sysresetreq()
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H A Dxlnx-pmu-iomod-intc.c34 #include "hw/intc/xlnx-pmu-iomod-intc.h"
36 #include "hw/qdev-properties.h"
339 s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE]; in xlnx_pmu_io_irq_update()
340 irq_out = !!s->regs[R_IRQ_PENDING]; in xlnx_pmu_io_irq_update()
344 qemu_set_irq(s->parent_irq, irq_out); in xlnx_pmu_io_irq_update()
349 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque); in xlnx_pmu_io_irq_enable_postw()
356 XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque); in xlnx_pmu_io_irq_ack_postw()
360 val &= s->regs[R_IRQ_STATUS]; in xlnx_pmu_io_irq_ack_postw()
361 s->regs[R_IRQ_STATUS] ^= val; in xlnx_pmu_io_irq_ack_postw()
363 /* Active level triggered interrupts stay high. */ in xlnx_pmu_io_irq_ack_postw()
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H A Darm_gicv3_cpuif.c18 #include "qemu/main-loop.h"
24 #include "target/arm/cpu-features.h"
37 return env->gicv3state; in icc_cs_from_env()
53 return 7 - cs->vprebits; in icv_min_vbpr()
59 int aprmax = 1 << (cs->vprebits - 5); in ich_num_aprs()
60 assert(aprmax <= ARRAY_SIZE(cs->ich_apr[0])); in ich_num_aprs()
114 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in read_vbpr()
117 return extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in read_vbpr()
136 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR0_SHIFT, in write_vbpr()
139 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VBPR1_SHIFT, in write_vbpr()
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/qemu/hw/m68k/
H A Dq800-glue.c25 #include "hw/m68k/q800-glue.h"
29 #include "hw/qdev-properties.h"
56 * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
65 * Level 7: Non-maskable: parity errors, RESET button
76 if (s->auxmode) { in GLUE_set_irq()
89 qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); in GLUE_set_irq()
101 /* Route to VIA2 instead, negative edge-triggered */ in GLUE_set_irq()
102 qemu_set_irq(s->irqs[GLUE_IRQ_ASC], !level); in GLUE_set_irq()
141 s->ipr |= 1 << irq; in GLUE_set_irq()
143 s->ipr &= ~(1 << irq); in GLUE_set_irq()
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/qemu/hw/i386/
H A Dacpi-common.c3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
28 #include "hw/acpi/aml-build.h"
32 #include "acpi-build.h"
33 #include "acpi-common.h"
38 uint32_t apic_id = apic_ids->cpus[uid].arch_id; in pc_madt_cpu_entry()
40 uint32_t flags = apic_ids->cpus[uid].cpu != NULL || force_enabled ? in pc_madt_cpu_entry()
50 /* Rev 1.0b, Table 5-13 Processor Local APIC Structure */ in pc_madt_cpu_entry()
103 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms)); in acpi_build_madt()
112 x86ms->pic != ON_OFF_AUTO_OFF ? 1 : 0 , 4); in acpi_build_madt()
114 for (i = 0; i < apic_ids->len; i++) { in acpi_build_madt()
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/qemu/hw/gpio/
H A Dpca9552.c4 * https://www.nxp.com/docs/en/application-note/AN264.pdf
6 * Copyright (c) 2017-2018, IBM Corporation.
7 * Copyright (c) 2020 Philippe Mathieu-Daudé
10 * later. See the COPYING file in the top-level directory.
17 #include "hw/qdev-properties.h"
57 return extract32(s->regs[reg], shift, 2); in pca955x_pin_get_config()
63 return (s->regs[PCA9552_INPUT1] << 8) | s->regs[PCA9552_INPUT0]; in pca955x_pins_get_status()
81 for (i = 0; i < k->pin_count; i++) { in pca955x_display_pins_status()
89 trace_pca955x_gpio_status(s->description, buf); in pca955x_display_pins_status()
92 for (i = 0; i < k->pin_count; i++) { in pca955x_display_pins_status()
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/qemu/include/hw/audio/
H A Dvirtio-snd.h13 * top-level directory.
21 #include "standard-headers/linux/virtio_ids.h"
22 #include "standard-headers/linux/virtio_snd.h"
24 #define TYPE_VIRTIO_SND "virtio-sound-device"
83 * The VirtIO sound spec reuses layouts and values from the High Definition
97 * buffer->elem = [[owned VQ element]];
101 * g_free(buffer->elem);
118 * bytes. The size of `data` is determined from the I/O message's read-only
119 * or write-only size when allocating VirtIOSoundPCMBuffer.
152 bool active; member
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/qemu/tests/qtest/
H A Dsse-timer-test.c18 #include "libqtest-single.h"
21 * SSE-123/SSE-300 timer in the mps3-an547 board, where it is driven
26 /* PERIPHNSPPC0 register in the SSE-300 Secure Access Configuration block */
109 * qtest accesses are always non-secure (no memory attributes), in test_timer()
142 /* Now exercise the auto-reload part of the timer */ in test_timer()
175 * CNTPCT and AIVAL registers, and check that their high halves in test_timer()
177 * non-autoinc mode because otherwise it takes forever as the in test_timer()
196 * scaling changes while it has an active timer. in test_timer_scale_change()
229 qtest_start("-machine mps3-an547"); in main()
231 qtest_add_func("/sse-timer/counter", test_counter); in main()
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/qemu/hw/net/
H A Dne2000.c4 * Copyright (c) 2003-2004 Fabrice Bellard
43 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
51 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
55 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
90 #define E8390_PAGE1 0x40 /* using the two high-order bits */
93 /* Bits in EN0_ISR - Interrupt status register */
122 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
128 s->isr = ENISR_RESET; in ne2000_reset()
129 memcpy(s->mem, &s->c.macaddr, 6); in ne2000_reset()
130 s->mem[14] = 0x57; in ne2000_reset()
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