accesses (full) in projects: linux-6.15

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/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n3/
D	l2_cache.json	4 …accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and … 8 …for data and instruction accesses. Accesses are for misses in the level 1 data cache or translatio… 20 … "Counts accesses to the level 2 cache due to instruction accesses. Level 2 cache is a unified cac… 24 …2 cache. Level 2 cache is a unified cache for data and instruction accesses. Accesses are for miss… 28 …accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction … 32 …accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction… 36 …accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache fo… 40 …accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache f… 64 …accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction… 68 …"PublicDescription": "Counts level 2 cache accesses that are due to a demand instruction cache acc… [all …]
D	memory.json	4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 8 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 12 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 16 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m… 20 …"PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred… 24 …"PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additiona… 32 …"PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS th… 36 …"PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by… 40 …"PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by… 48 … "PublicDescription": "Counts the number of outstanding loads or memory read accesses per cycle." [all …]
D	metrics.json	145 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 147 "ScaleUnit": "100percent of TLB accesses" 268 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 270 "ScaleUnit": "100percent of TLB accesses" 275 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 277 "ScaleUnit": "100percent of cache accesses" 282 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 289 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 291 "ScaleUnit": "100percent of TLB accesses" 296 …"BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thous… [all …]
D	l3_cache.json	`8 "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 12 …accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for mis… 16 …accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instru… 24 "PublicDescription": "Counts level 3 cache accesses that missed in the level 3 cache."`
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 44 …accesses triggered by a data translation table walk and performing an update of a translation tabl… 48 … of memory accesses triggered by an instruction translation table walk and performing an update of… 52 …accesses triggered by a demand data translation table walk and performing a read of a translation … 56 …er of memory accesses triggered by an instruction translation table walk and performing a read of …
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-v3/
D	l2_cache.json	4 …accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and … 8 …for data and instruction accesses. Accesses are for misses in the level 1 data cache or translatio… 16 …accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction … 20 …accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction… 24 …accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache fo… 28 …accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache f… 43 …"PublicDescription": "Counts level 2 cache accesses due to level 1 data cache hardware prefetcher.… 60 …accesses from any load/store operations. Level 2 cache is a unified cache for data and instruction… 64 …"PublicDescription": "Counts level 2 data cache accesses generated by software preload or prefetch… 68 …for data and instruction accesses. Accesses are for misses in the level 1 data cache or translatio… [all …]
D	memory.json	4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m… 24 …"PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred… 28 …"PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additiona… 36 …"PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS th… 40 …"PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by… 44 …"PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by… 52 … "PublicDescription": "Counts the number of outstanding loads or memory read accesses per cycle." [all …]
D	metrics.json	145 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 147 "ScaleUnit": "100percent of TLB accesses" 268 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 270 "ScaleUnit": "100percent of TLB accesses" 275 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 277 "ScaleUnit": "100percent of cache accesses" 282 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 289 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 291 "ScaleUnit": "100percent of TLB accesses" 296 …"BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thous… [all …]
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data… [all …]
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
D	l2_cache.json	4 …accesses to the level 2 cache due to data accesses. Level 2 cache is a unified cache for data and … 8 …for data and instruction accesses. Accesses are for misses in the level 1 data cache or translatio… 20 …accesses due to memory read operations. Level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. Level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. Level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. Level 2 cache is a unified cache f…
D	metrics.json	55 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 57 "ScaleUnit": "100percent of TLB accesses" 94 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 96 "ScaleUnit": "100percent of TLB accesses" 101 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 103 "ScaleUnit": "100percent of cache accesses" 108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 115 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 117 "ScaleUnit": "100percent of TLB accesses" 122 …"BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thous… [all …]
D	memory.json	4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m… 24 …"PublicDescription": "Counts the number of memory read and write accesses in a cycle that incurred… 28 …"PublicDescription": "Counts the number of memory read accesses in a cycle that incurred additiona… 36 …"PublicDescription": "Counts the number of memory read and write accesses counted by MEM_ACCESS th… 40 …"PublicDescription": "Counts the number of memory read accesses in a cycle that are tag checked by… 44 …"PublicDescription": "Counts the number of memory write accesses in a cycle that is tag checked by…
D	l3_cache.json	`8 "PublicDescription": "Counts level 3 accesses that receive data from outside the L3 cache." 12 …accesses. Level 3 cache is a unified cache for data and instruction accesses. Accesses are for mis… 16 …accesses caused by any memory read operation. Level 3 cache is a unified cache for data and instru…`
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
D	l2_cache.json	4 …accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for mis… 8 …e for data and instruction accesses. Accesses are for misses in the level 1 caches or translation … 20 …accesses due to memory read operations. level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache f…
D	metrics.json	47 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 82 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 89 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 103 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 110 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 117 … the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction… 124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 131 …res the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instructio… 138 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… [all …]
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
D	memory.json	`4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m…`
/linux-6.15/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
D	l2_cache.json	4 …accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are for mis… 8 …e for data and instruction accesses. Accesses are for misses in the level 1 caches or translation … 20 …accesses due to memory read operations. level 2 cache is a unified cache for data and instruction … 24 …accesses due to memory write operations. level 2 cache is a unified cache for data and instruction… 28 …accesses due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache fo… 32 …accesses due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache f…
D	metrics.json	54 …lks to the total number of data TLB accesses. This gives an indication of the effectiveness of the… 93 … total number of instruction TLB accesses. This gives an indication of the effectiveness of the in… 100 …c measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cac… 107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 114 …tric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TL… 121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… 128 … the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction… 135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 142 …res the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instructio… 149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe… [all …]
D	tlb.json	8 …accesses that resulted in TLB refills. If there are multiple misses in the TLB that are resolved b… 12 …"PublicDescription": "Counts level 1 data TLB accesses caused by any memory load or store operatio… 16 …ion TLB accesses, whether the access hits or misses in the TLB. This event counts both demand acce… 24 …"PublicDescription": "Counts level 2 TLB accesses except those caused by TLB maintenance operation… 36 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 40 … counts for refills caused by preload instructions or hardware prefetch accesses. This event count… 44 …"PublicDescription": "Counts level 1 data TLB accesses caused by memory read operations. This even… 48 …"PublicDescription": "Counts any L1 data side TLB accesses caused by memory write operations. This… 60 …"PublicDescription": "Counts level 2 TLB accesses caused by memory read operations from both data … 64 …"PublicDescription": "Counts level 2 TLB accesses caused by memory write operations from both data…
D	memory.json	`4 …accesses issued by the CPU load store unit, where those accesses are issued due to load or store o… 12 …"PublicDescription": "Counts accesses to another chip, which is implemented as a different CMN mes… 16 …accesses issued by the CPU due to load operations. The event counts any memory load access, no mat… 20 …accesses issued by the CPU due to store operations. The event counts any memory store access, no m…`
/linux-6.15/tools/perf/Documentation/
D	perf-c2c.txt	37 for cachelines with highest contention - highest number of HITM accesses. 196 - cacheline percentage of all Remote/Local HITM accesses 199 - cacheline percentage of all peer accesses 208 - sum of all cachelines accesses 211 - sum of all load accesses 214 - sum of all store accesses 217 L1Hit - store accesses that hit L1 218 L1Miss - store accesses that missed L1 219 N/A - store accesses with memory level is not available 225 - count of LLC load accesses, includes LLC hits and LLC HITMs [all …]
/linux-6.15/tools/memory-model/Documentation/
D	ordering.txt	15 2. Ordered memory accesses. These operations order themselves 16 against some or all of the CPU's prior accesses or some or all 17 of the CPU's subsequent accesses, depending on the subcategory 20 3. Unordered accesses, as the name indicates, have no ordering 48 a device driver, which must correctly order accesses to a physical 68 accesses against all subsequent accesses from the viewpoint of all CPUs. 89 CPU's accesses into three groups: 242 Ordered Memory Accesses 245 The Linux kernel provides a wide variety of ordered memory accesses: 264 of the CPU's prior memory accesses. Release operations often provide [all …]
/linux-6.15/Documentation/dev-tools/
D	kcsan.rst	78 the racing thread, but could also occur due to e.g. DMA accesses. Such reports 85 It may be desirable to disable data race detection for specific accesses, 90 any data races due to accesses in ``expr`` should be ignored and resulting 92 `"Marking Shared-Memory Accesses" in the LKMM`_ for more information. 95 to document that all data races due to accesses to a variable are intended 124 .. _"Marking Shared-Memory Accesses" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/t… 138 accesses are aligned writes up to word size. 200 In an execution, two memory accesses form a data race if they conflict, 204 Accesses and Data Races" in the LKMM`_. 206 .. _"Plain Accesses and Data Races" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/to… [all …]

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