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/linux/include/sound/ac97/
H A Dcontroller.h1 /* SPDX-License-Identifier: GPL-2.0
18 * struct ac97_controller - The AC97 controller of the AC-Link
19 * @ops: the AC97 operations.
21 * @adap: the shell device ac97-%d, ie. ac97 adapter
24 * @parent: the device providing the AC97 controller.
25 * @codecs: the 4 possible AC97 codecs (NULL if none found).
28 * This structure is internal to AC97 bus, and should not be used by the
43 * struct ac97_controller_ops - The AC97 operations
44 * @reset: Cold reset of the AC97 AC-Link.
45 * @warm_reset: Warm reset of the AC97 AC-Link.
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/linux/Documentation/devicetree/bindings/sound/
H A Dloongson,ls1b-ac97.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/loongson,ls1b-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 AC97 Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 The Loongson-1 AC97 controller supports 2-channel stereo output and input.
17 - $ref: dai-common.yaml#
22 - const: loongson,ls1b-ac97
23 - items:
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H A Dnvidia,tegra20-ac97.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra20-ac97.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 AC97 controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra20-ac97
23 reset-names:
24 const: ac97
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H A Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
24 "fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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H A Dmarvell,pxa2xx-ac97.txt3 This descriptions matches the AC97 controller found in pxa2xx and pxa3xx series.
6 - compatible: should be one of the following:
7 "marvell,pxa250-ac97"
8 "marvell,pxa270-ac97"
9 "marvell,pxa300-ac97"
10 - reg: device MMIO address space
11 - interrupts: single interrupt generated by AC97 IP
12 - clocks: input clock of the AC97 IP, refer to clock-bindings.txt
15 - pinctrl-names, pinctrl-0: refer to pinctrl-bindings.txt
16 - reset-gpios: gpio used for AC97 reset, refer to gpio.txt
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H A Dac97-bus.txt1 Generic AC97 Device Properties
3 This documents describes the devicetree bindings for an ac97 controller child
4 node describing ac97 codecs.
7 -compatible : Must be "ac97,vendor_id1,vendor_id2
10 -reg : Must be the ac97 codec number, between 0 and 3
13 ac97: sound@40500000 {
14 compatible = "marvell,pxa270-ac97";
17 reset-gpios = <&gpio 95 GPIO_ACTIVE_HIGH>;
18 #sound-dai-cells = <1>;
19 pinctrl-names = "default";
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H A Datmel_ac97c.txt1 * Atmel AC97 controller
4 - compatible: "atmel,at91sam9263-ac97c"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain AC97 interrupt
7 - ac97-gpios: Please refer to soc-ac97link.txt, only ac97-reset is used
9 - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt
13 compatible = "atmel,at91sam9263-ac97c";
14 pinctrl-names = "default";
15 pinctrl-0 = <&pinctrl_ac97>;
19 ac97-gpios = <&pioB 0 0 &pioB 2 0 &pioC 29 GPIO_ACTIVE_LOW>;
H A Dnvidia,tegra-audio-wm9712.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-wm9712.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-wm9712([-_][a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-wm9712
22 nvidia,audio-routing:
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/linux/sound/ac97/
H A Dbus.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <sound/ac97/codec.h>
20 #include <sound/ac97/controller.h>
21 #include <sound/ac97/regs.h>
41 return -ENODEV; in ac97_unbound_ctrl_write()
47 return -ENODEV; in ac97_unbound_ctrl_read()
63 return ERR_PTR(-EINVAL); in ac97_codec_find()
65 return ac97_ctrl->codecs[codec_num]; in ac97_codec_find()
74 char compat[] = "ac97,0000,0000"; in ac97_of_get_child_device()
76 snprintf(compat, sizeof(compat), "ac97,%04x,%04x", in ac97_of_get_child_device()
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H A Dsnd_ac97_compat.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <sound/ac97/codec.h>
9 #include <sound/ac97/compat.h>
10 #include <sound/ac97/controller.h>
20 static void compat_ac97_reset(struct snd_ac97 *ac97) in compat_ac97_reset() argument
22 struct ac97_codec_device *adev = to_ac97_device(ac97->private_data); in compat_ac97_reset()
23 struct ac97_controller *actrl = adev->ac97_ctrl; in compat_ac97_reset()
25 if (actrl->ops->reset) in compat_ac97_reset()
26 actrl->ops->reset(actrl); in compat_ac97_reset()
29 static void compat_ac97_warm_reset(struct snd_ac97 *ac97) in compat_ac97_warm_reset() argument
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/linux/sound/soc/au1x/
H A Dpsc-ac97.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * (c) 2007-2009 MSC Vertriebsges.m.b.H.,
8 * Au1xxx-PSC AC97 glue.
22 #include <asm/mach-au1x00/au1000.h>
23 #include <asm/mach-au1x00/au1xxx_psc.h>
54 /* this could theoretically work, but ac97->bus->card->private_data can be NULL
60 struct snd_soc_card *c = x->bus->card->private_data;
61 return snd_soc_dai_get_drvdata(c->snd_soc_rtd_to_cpu(rtd, 0));
70 /* AC97 controller reads codec register */
71 static unsigned short au1xpsc_ac97_read(struct snd_ac97 *ac97, in au1xpsc_ac97_read() argument
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 Controllers in AC97 and I2S mode, and the Descriptor-Based DMA
13 Controller (DBDMA) as found on the Au12xx/Au13xx/Au1550 SoC.
31 This is a driver set for the AC97 unit and the
32 old DMA controller as found on the Au1000/Au1500/Au1100 chips.
53 Select this option to enable AC97 audio on the early DB1x00 series
65 Select this option to enable audio (AC97 and I2S) on the
H A Dac97c.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Au1000/Au1500/Au1100 AC97C controller driver for ASoC
8 * Charles Eidsness <charles@cooper-street.com>
23 #include <asm/mach-au1x00/au1000.h>
74 return __raw_readl(ctx->mmio + reg); in RD()
79 __raw_writel(v, ctx->mmio + reg); in WR()
83 static unsigned short au1xac97c_ac97_read(struct snd_ac97 *ac97, in au1xac97c_ac97_read() argument
86 struct au1xpsc_audio_data *ctx = ac97_to_ctx(ac97); in au1xac97c_ac97_read()
93 mutex_lock(&ctx->lock); in au1xac97c_ac97_read()
96 while ((RD(ctx, AC97_STATUS) & STAT_CP) && --tmo) in au1xac97c_ac97_read()
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/linux/sound/soc/loongson/
H A Dloongson1_ac97.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AC97 Controller Driver for Loongson-1 SoC
9 #include <linux/dma-mapping.h>
20 /* Loongson-1 AC97 Controller Registers */
106 static void ls1x_ac97_reset(struct snd_ac97 *ac97) in ls1x_ac97_reset() argument
110 regmap_write(ls1x_ac97->regmap, AC97_CSR, CSR_RST_FORCE); in ls1x_ac97_reset()
111 regmap_read_poll_timeout(ls1x_ac97->regmap, AC97_CSR, val, in ls1x_ac97_reset()
115 static void ls1x_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) in ls1x_ac97_write() argument
120 regmap_write(ls1x_ac97->regmap, AC97_CRAC, tmp); in ls1x_ac97_write()
121 ret = regmap_read_poll_timeout(ls1x_ac97->regmap, AC97_INTRAW, tmp, in ls1x_ac97_write()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 loongson I2S controller.
14 loongson I2S controller.
17 tristate "Loongson I2S-PCI Device Driver"
23 Loongson I2S controller.
25 The controller is found in loongson bridge chips or SoCs,
29 tristate "Loongson I2S-PLAT Device Driver"
35 Loongson I2S controller.
37 The controller work as a platform device, we can found it in
38 Loongson-2K1000 SoCs.
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/linux/Documentation/sound/soc/
H A Ddai.rst6 SoC controllers and portable audio CODECs today, namely AC97, I2S and PCM.
9 AC97 chapter
12 AC97 is a five wire interface commonly found on many PC sound cards. It is
16 frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
19 The AC97 specification can be found at :
29 controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
35 I2S has several different operating modes:-
58 Common PCM operating modes:-
/linux/arch/powerpc/boot/dts/
H A Dpcm030.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
13 &gpt0 { fsl,has-wdt; };
14 &gpt2 { gpio-controller; };
15 &gpt3 { gpio-controller; };
16 &gpt4 { gpio-controller; };
17 &gpt5 { gpio-controller; };
18 &gpt6 { gpio-controller; };
19 &gpt7 { gpio-controller; };
26 audioplatform: psc@2000 { /* PSC1 in ac97 mode */
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H A Dpcm032.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
5 * Copyright (C) 2006-2009 Pengutronix
11 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; };
14 &gpt4 { gpio-controller; };
15 &gpt5 { gpio-controller; };
16 &gpt6 { gpio-controller; };
17 &gpt7 { gpio-controller; };
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H A Dlite5200b.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007 Secret Lab Technologies Ltd.
11 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; };
20 compatible = "gpio-leds";
26 linux,default-trigger = "heartbeat";
40 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
41 cell-index = <0>;
64 // PSC2 in ac97 mode example
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
23 uart1(cts), lcd-spi(cs1), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
40 mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
41 ac97-1(sysclko)
42 mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
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/linux/sound/atmel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Atmel AC97 Controller (AC97C) driver"
11 ALSA sound driver for the Atmel AC97 controller.
/linux/sound/soc/pxa/
H A Dpxa2xx-ac97.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
15 #include <linux/dma/pxa-dma.h>
17 #include <sound/ac97/controller.h>
21 #include <sound/pxa2xx-lib.h>
24 #include <linux/platform_data/asoc-pxa.h>
28 #define MCDR 0x0060 /* Mic-in FIFO Data Register */
98 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in pxa2xx_ac97_hifi_startup()
113 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in pxa2xx_ac97_aux_startup()
126 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in pxa2xx_ac97_mic_startup()
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/linux/sound/soc/tegra/
H A Dtegra20_ac97.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * tegra20_ac97.c - Tegra20 AC97 platform driver
32 #define DRV_NAME "tegra20-ac97"
36 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97) in tegra20_ac97_codec_reset() argument
46 gpiod_set_value(workdata->reset_gpio, 1); in tegra20_ac97_codec_reset()
49 gpiod_set_value(workdata->reset_gpio, 0); in tegra20_ac97_codec_reset()
55 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback); in tegra20_ac97_codec_reset()
62 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97) in tegra20_ac97_codec_warm_reset() argument
69 * the controller cmd is not working, have to toggle sync line in tegra20_ac97_codec_warm_reset()
72 gpiod_direction_output(workdata->sync_gpio, 1); in tegra20_ac97_codec_warm_reset()
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/linux/Documentation/devicetree/bindings/dma/
H A Dcirrus,ep9301-dma-m2p.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/cirrus,ep9301-dma-m2p.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cirrus Logic ep93xx SoC M2P DMA controller
10 - Alexander Sverdlin <alexander.sverdlin@gmail.com>
11 - Nikita Shubin <nikita.shubin@maquefel.me>
14 - $ref: dma-controller.yaml#
19 - const: cirrus,ep9301-dma-m2p
20 - items:
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/linux/sound/soc/renesas/
H A Dhac.c1 // SPDX-License-Identifier: GPL-2.0
3 // Hitachi Audio Controller (AC97) support for SH7760/SH7780
10 /* BIG FAT FIXME: although the SH7760 has 2 independent AC97 units, only
13 * to edit the code a bit to use the other AC97 unit. --mlau
40 #define CR_CR (1 << 15) /* "codec-ready" indicator */
44 #define CR_ST (1 << 5) /* AC97 link start bit */
46 #define CSAR_RD (1 << 19) /* AC97 data read bit */
69 /* manual-suggested AC97 codec access timeouts (us) */
94 #define HACREG(reg) (*(unsigned long *)(hac->mmio + (reg)))
97 * AC97 read/write flow as outlined in the SH7760 manual (pages 903-906)
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