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/linux-5.10/tools/perf/pmu-events/arch/nds32/n13/
Datcpmu.json6 "BriefDescription": "V3 Conditional branch"
12 "BriefDescription": "V3 Taken Conditional branch"
18 "BriefDescription": "V3 Prefetch Instruction"
24 "BriefDescription": "V3 RET Inst"
30 "BriefDescription": "V3 JR(non-RET) instructions"
36 "BriefDescription": "V3 JAL/JRAL instructions"
42 "BriefDescription": "V3 NOP instructions"
48 "BriefDescription": "V3 SCW instructions"
54 "BriefDescription": "V3 ISB/DSB instructions"
60 "BriefDescription": "V3 CCTL instructions"
[all …]
/linux-5.10/drivers/pci/controller/
Dpci-v3-semi.c3 * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
251 * The V3 PCI interface chip in Integrator provides several windows from
264 * There are three V3 windows, each described by a pair of V3 registers.
291 * The V3 chip translates an address by checking its range within
295 * LB_BASE1/LB_MAP1, the V3 will use the translation from
315 struct v3_pci *v3 = bus->sysdata; in v3_map_bus() local
367 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
369 v3->base + V3_LB_BASE0); in v3_map_bus()
375 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
377 v3->base + V3_LB_BASE1); in v3_map_bus()
[all …]
/linux-5.10/include/uapi/linux/
Dnfs.h47 NFS_OK = 0, /* v2 v3 v4 */
48 NFSERR_PERM = 1, /* v2 v3 v4 */
49 NFSERR_NOENT = 2, /* v2 v3 v4 */
50 NFSERR_IO = 5, /* v2 v3 v4 */
51 NFSERR_NXIO = 6, /* v2 v3 v4 */
52 NFSERR_EAGAIN = 11, /* v2 v3 */
53 NFSERR_ACCES = 13, /* v2 v3 v4 */
54 NFSERR_EXIST = 17, /* v2 v3 v4 */
55 NFSERR_XDEV = 18, /* v3 v4 */
56 NFSERR_NODEV = 19, /* v2 v3 v4 */
[all …]
/linux-5.10/lib/
Dsiphash.c24 v2 += v3; v3 = rol64(v3, 16); v3 ^= v2; \
25 v0 += v3; v3 = rol64(v3, 21); v3 ^= v0; \
33 u64 v3 = 0x7465646279746573ULL; \
35 v3 ^= key->key[1]; \
41 v3 ^= b; \
50 return (v0 ^ v1) ^ (v2 ^ v3);
60 v3 ^= m; in __siphash_aligned()
93 v3 ^= m; in __siphash_unaligned()
126 v3 ^= first; in siphash_1u64()
143 v3 ^= first; in siphash_2u64()
[all …]
Dxxhash.c112 uint32_t v3 = seed + 0; in xxh32() local
120 v3 = xxh32_round(v3, get_unaligned_le32(p)); in xxh32()
127 xxh_rotl32(v3, 12) + xxh_rotl32(v4, 18); in xxh32()
182 uint64_t v3 = seed + 0; in xxh64() local
190 v3 = xxh64_round(v3, get_unaligned_le64(p)); in xxh64()
197 xxh_rotl64(v3, 12) + xxh_rotl64(v4, 18); in xxh64()
200 h64 = xxh64_merge_round(h64, v3); in xxh64()
250 state.v3 = seed + 0; in xxh32_reset()
264 state.v3 = seed + 0; in xxh64_reset()
297 state->v3 = xxh32_round(state->v3, get_unaligned_le32(p32)); in xxh32_update()
[all …]
Drandom32.c337 unsigned long v3; member
355 * - Rather than returning v0^v1^v2^v3, return v1+v3.
356 * If you look at the SipHash round, the last operation on v3 is
357 * "v3 ^= v0", so "v0 ^ v3" just undoes that, a waste of time.
365 unsigned long v0 = s->v0, v1 = s->v1, v2 = s->v2, v3 = s->v3; in siprand_u32() local
368 v3 ^= n; in siprand_u32()
369 PRND_SIPROUND(v0, v1, v2, v3); in siprand_u32()
370 PRND_SIPROUND(v0, v1, v2, v3); in siprand_u32()
372 s->v0 = v0; s->v1 = v1; s->v2 = v2; s->v3 = v3; in siprand_u32()
373 return v1 + v3; in siprand_u32()
[all …]
/linux-5.10/arch/s390/include/asm/
Dvx-insn.h100 .ifc \vxr,%v3
197 * @v3: Third vector register designated operand
200 .macro RXB rxb v1 v2=0 v3=0 v4=0
208 .if \v3 & 0x10
221 * @v3: Third vector register designated operand (for RXB)
224 .macro MRXB m v1 v2=0 v3=0 v4=0
226 RXB rxb, \v1, \v2, \v3, \v4
236 * @v3: Third vector register designated operand (for RXB)
239 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
240 MRXB \m, \v1, \v2, \v3, \v4
[all …]
/linux-5.10/arch/arm64/lib/
Dxor-neon.c19 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_2() local
27 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_2()
33 vst1q_u64(dp1 + 6, v3); in xor_arm64_neon_2()
47 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_3() local
55 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_3()
61 v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); in xor_arm64_neon_3()
67 vst1q_u64(dp1 + 6, v3); in xor_arm64_neon_3()
83 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_4() local
91 v3 = veorq_u64(vld1q_u64(dp1 + 6), vld1q_u64(dp2 + 6)); in xor_arm64_neon_4()
97 v3 = veorq_u64(v3, vld1q_u64(dp3 + 6)); in xor_arm64_neon_4()
[all …]
/linux-5.10/include/linux/
Dprandom.h30 #define PRND_SIPROUND(v0, v1, v2, v3) ( \ argument
31 v0 += v1, v1 = rol64(v1, 13), v2 += v3, v3 = rol64(v3, 16), \
32 v1 ^= v0, v0 = rol64(v0, 32), v3 ^= v2, \
33 v0 += v3, v3 = rol64(v3, 21), v2 += v1, v1 = rol64(v1, 17), \
34 v3 ^= v0, v1 ^= v2, v2 = rol64(v2, 32) \
46 #define PRND_SIPROUND(v0, v1, v2, v3) ( \ argument
47 v0 += v1, v1 = rol32(v1, 5), v2 += v3, v3 = rol32(v3, 8), \
48 v1 ^= v0, v0 = rol32(v0, 16), v3 ^= v2, \
49 v0 += v3, v3 = rol32(v3, 7), v2 += v1, v1 = rol32(v1, 13), \
50 v3 ^= v0, v1 ^= v2, v2 = rol32(v2, 16) \
/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
76 FN(reg, f3), v3)
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
82 FN(reg, f3), v3,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
90 FN(reg, f3), v3,\
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
99 FN(reg, f3), v3,\
104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
109 FN(reg, f3), v3,\
[all …]
/linux-5.10/arch/arm64/crypto/
Daes-modes.S26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
63 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
67 st1 {v0.16b-v3.16b}, [x0], #64
94 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 ct blocks */
98 st1 {v0.16b-v3.16b}, [x0], #64
145 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
152 eor v3.16b, v3.16b, v2.16b
[all …]
Dsm3-ce-core.S88 0: ld1 {v0.16b-v3.16b}, [x1], #64
97 CPU_LE( rev32 v3.16b, v3.16b )
101 qround a, v0, v1, v2, v3, v4
102 qround a, v1, v2, v3, v4, v0
103 qround a, v2, v3, v4, v0, v1
104 qround a, v3, v4, v0, v1, v2
108 qround b, v4, v0, v1, v2, v3
109 qround b, v0, v1, v2, v3, v4
110 qround b, v1, v2, v3, v4, v0
111 qround b, v2, v3, v4, v0, v1
[all …]
Dchacha-neon-core.S32 * registers v0-v3. It performs matrix operations on four words in parallel,
47 eor v3.16b, v3.16b, v0.16b
48 rev32 v3.8h, v3.8h
51 add v2.4s, v2.4s, v3.4s
58 eor v3.16b, v3.16b, v0.16b
59 tbl v3.16b, {v3.16b}, v12.16b
62 add v2.4s, v2.4s, v3.4s
72 ext v3.16b, v3.16b, v3.16b, #12
76 eor v3.16b, v3.16b, v0.16b
77 rev32 v3.8h, v3.8h
[all …]
Daes-ce-core.S18 mov v3.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
25 aese v0.16b, v3.16b
31 ld1 {v3.4s}, [x0], #16
34 eor v0.16b, v0.16b, v3.16b
46 mov v3.16b, v1.16b
49 ld1 {v3.4s}, [x0], #16
53 aesd v0.16b, v3.16b
59 ld1 {v3.4s}, [x0], #16
62 eor v0.16b, v0.16b, v3.16b
Daes-ce-ccm-core.S32 1: ld1 {v3.4s}, [x4] /* load first round key */
39 mov v5.16b, v3.16b
41 2: mov v4.16b, v3.16b
45 4: ld1 {v3.4s}, [x6], #16 /* load next round key */
50 aese v0.16b, v3.16b
91 ld1 {v3.4s}, [x2], #16 /* load first round key */
98 mov v5.16b, v3.16b
100 0: mov v4.16b, v3.16b
106 2: ld1 {v3.4s}, [x2], #16 /* load next round key */
113 aese v0.16b, v3.16b
[all …]
/linux-5.10/arch/powerpc/lib/
Dxor_vmx.c75 DEFINE(v3); in __xor_altivec_3()
81 LOAD(v3); in __xor_altivec_3()
83 XOR(v1, v3); in __xor_altivec_3()
88 v3 += 4; in __xor_altivec_3()
98 DEFINE(v3); in __xor_altivec_4()
105 LOAD(v3); in __xor_altivec_4()
108 XOR(v3, v4); in __xor_altivec_4()
109 XOR(v1, v3); in __xor_altivec_4()
114 v3 += 4; in __xor_altivec_4()
125 DEFINE(v3); in __xor_altivec_5()
[all …]
/linux-5.10/drivers/char/mwave/
Dmwavedd.h89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument
96 printk(s,v1,v2,v3,v4); \
99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
[all …]
/linux-5.10/include/pcmcia/
Ddevice_id.h34 #define PCMCIA_DEVICE_PROD_ID3(v3, vh3) { \ argument
36 .prod_id = { NULL, NULL, (v3), NULL }, \
45 #define PCMCIA_DEVICE_PROD_ID13(v1, v3, vh1, vh3) { \ argument
48 .prod_id = { (v1), NULL, (v3), NULL }, \
57 #define PCMCIA_DEVICE_PROD_ID123(v1, v2, v3, vh1, vh2, vh3) { \ argument
61 .prod_id = { (v1), (v2), (v3), NULL },\
71 #define PCMCIA_DEVICE_PROD_ID134(v1, v3, v4, vh1, vh3, vh4) { \ argument
75 .prod_id = { (v1), NULL, (v3), (v4) }, \
78 #define PCMCIA_DEVICE_PROD_ID1234(v1, v2, v3, v4, vh1, vh2, vh3, vh4) { \ argument
83 .prod_id = { (v1), (v2), (v3), (v4) }, \
[all …]
/linux-5.10/Documentation/devicetree/bindings/hwmon/
Dltc2990.txt15 2: V1-V2, V3, V4
16 3: TR1, V3, V4
17 4: TR1, V3-V4
19 6: V1-V2, V3-V4
20 7: V1, V2, V3, V4
27 2: TR2, V3 or V3-V4 only per mode
35 lltc,meas-mode = <7 3>; /* V1, V2, V3, V4 */
/linux-5.10/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
59 using pads at 3V3 and 1V8 levels.
62 - nvidia,pad-autocal-pull-up-offset-3v3,
63 nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
68 - nvidia,pad-autocal-pull-up-offset-3v3-timeout,
69 nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
116 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
119 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
120 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
[all …]
/linux-5.10/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c238 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; member
278 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); in amdgpu_atombios_crtc_program_ss()
279 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in amdgpu_atombios_crtc_program_ss()
282 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; in amdgpu_atombios_crtc_program_ss()
285 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; in amdgpu_atombios_crtc_program_ss()
288 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; in amdgpu_atombios_crtc_program_ss()
293 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in amdgpu_atombios_crtc_program_ss()
294 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in amdgpu_atombios_crtc_program_ss()
295 args.v3.ucEnable = enable; in amdgpu_atombios_crtc_program_ss()
302 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; member
[all …]
Datombios_encoders.c566 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
613 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
645 args.v3.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
646 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dig_encoder()
648 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
650 args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); in amdgpu_atombios_encoder_setup_dig_encoder()
652 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) in amdgpu_atombios_encoder_setup_dig_encoder()
653 args.v3.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_encoder()
655 args.v3.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
657 args.v3.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_encoder()
[all …]
/linux-5.10/arch/arm64/boot/dts/freescale/
Dqoriq-fman3-0.dtsi3 * QorIQ FMan v3 device tree
31 compatible = "fsl,fman-v3-port-oh";
37 compatible = "fsl,fman-v3-port-oh";
43 compatible = "fsl,fman-v3-port-oh";
49 compatible = "fsl,fman-v3-port-oh";
55 compatible = "fsl,fman-v3-port-oh";
61 compatible = "fsl,fman-v3-port-oh";
/linux-5.10/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S163 vxor v3,v3,v3
277 vxor v3,v3,v11
328 vxor v3,v3,v11
353 vxor v3,v3,v11
369 vsldoi v3,v3,zeroes,4
399 vxor v19,v3,v11
428 lvx v3,off48,r3
438 VPMSUMW(v3,v19,v3)
498 vxor v2,v2,v3
646 lvx v3,off48,r4
[all …]
/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f3), v3)
76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f3), v3, \
97 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ argument
101 FN(reg, f3), v3)
103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
107 FN(reg, f3), v3, \

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