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/linux-5.10/drivers/usb/host/
Dxhci-tegra.c3 * NVIDIA Tegra xHCI host controller driver
19 #include <linux/phy/tegra/xusb.h>
30 #include <soc/tegra/pmc.h>
278 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset) in fpci_readl() argument
280 return readl(tegra->fpci_base + offset); in fpci_readl()
283 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value, in fpci_writel() argument
286 writel(value, tegra->fpci_base + offset); in fpci_writel()
289 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset) in ipfs_readl() argument
291 return readl(tegra->ipfs_base + offset); in ipfs_readl()
294 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, in ipfs_writel() argument
[all …]
Dehci-tegra.c3 * EHCI-compliant USB host controller driver for NVIDIA Tegra SoCs
35 #define DRIVER_DESC "Tegra EHCI driver"
36 #define DRV_NAME "tegra-ehci"
55 struct tegra_ehci_hcd *tegra = in tegra_reset_usb_controller() local
86 err = reset_control_deassert(tegra->rst); in tegra_reset_usb_controller()
90 err = reset_control_assert(tegra->rst); in tegra_reset_usb_controller()
96 err = reset_control_deassert(tegra->rst); in tegra_reset_usb_controller()
178 struct tegra_ehci_hcd *tegra = (struct tegra_ehci_hcd *)ehci->priv; in tegra_ehci_hub_control() local
190 if (tegra->port_resuming && !(temp & PORT_SUSPEND)) { in tegra_ehci_hub_control()
192 tegra->port_resuming = 0; in tegra_ehci_hub_control()
[all …]
/linux-5.10/drivers/devfreq/
Dtegra30-devfreq.c3 * A devfreq driver for NVIDIA Tegra SoCs
193 static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset) in actmon_readl() argument
195 return readl_relaxed(tegra->regs + offset); in actmon_readl()
198 static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset) in actmon_writel() argument
200 writel_relaxed(val, tegra->regs + offset); in actmon_writel()
226 static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_avg_wmark() argument
229 u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ; in tegra_devfreq_update_avg_wmark()
230 u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms; in tegra_devfreq_update_avg_wmark()
240 static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra, in tegra_devfreq_update_wmark() argument
243 u32 val = tegra->cur_freq * tegra->devfreq->profile->polling_ms; in tegra_devfreq_update_wmark()
[all …]
Dtegra20-devfreq.c18 #include <soc/tegra/mc.h>
40 struct tegra_devfreq *tegra = dev_get_drvdata(dev); in tegra_devfreq_target() local
41 struct devfreq *devfreq = tegra->devfreq; in tegra_devfreq_target()
53 err = clk_set_min_rate(tegra->emc_clock, rate); in tegra_devfreq_target()
57 err = clk_set_rate(tegra->emc_clock, 0); in tegra_devfreq_target()
64 clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq); in tegra_devfreq_target()
72 struct tegra_devfreq *tegra = dev_get_drvdata(dev); in tegra_devfreq_get_dev_status() local
84 stat->busy_time = readl_relaxed(tegra->regs + MC_STAT_EMC_COUNT); in tegra_devfreq_get_dev_status()
85 stat->total_time = readl_relaxed(tegra->regs + MC_STAT_EMC_CLOCKS) / 8; in tegra_devfreq_get_dev_status()
86 stat->current_frequency = clk_get_rate(tegra->emc_clock); in tegra_devfreq_get_dev_status()
[all …]
/linux-5.10/drivers/ata/
Dahci_tegra.c20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
179 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks() local
182 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
183 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
185 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
191 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init() local
203 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
205 val = readl(tegra->sata_regs + in tegra124_ahci_init()
[all …]
/linux-5.10/drivers/clk/tegra/
Dclk-tegra124-emc.c3 * drivers/clk/tegra/clk-emc.c
23 #include <soc/tegra/fuse.h>
24 #include <soc/tegra/emc.h>
90 struct tegra_clk_emc *tegra; in emc_recalc_rate() local
93 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_recalc_rate()
101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()
114 struct tegra_clk_emc *tegra; in emc_determine_rate() local
119 tegra = container_of(hw, struct tegra_clk_emc, hw); in emc_determine_rate()
121 for (k = 0; k < tegra->num_timings; k++) { in emc_determine_rate()
122 if (tegra->timings[k].ram_code == ram_code) in emc_determine_rate()
[all …]
/linux-5.10/sound/soc/tegra/
DMakefile2 # Tegra platform Support
3 snd-soc-tegra-pcm-objs := tegra_pcm.o
4 snd-soc-tegra-utils-objs += tegra_asoc_utils.o
17 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-pcm.o
18 obj-$(CONFIG_SND_SOC_TEGRA) += snd-soc-tegra-utils.o
31 # Tegra machine Support
32 snd-soc-tegra-rt5640-objs := tegra_rt5640.o
33 snd-soc-tegra-rt5677-objs := tegra_rt5677.o
34 snd-soc-tegra-wm8753-objs := tegra_wm8753.o
35 snd-soc-tegra-wm8903-objs := tegra_wm8903.o
[all …]
DKconfig3 tristate "SoC Audio for the Tegra System-on-Chip"
10 Say Y or M here if you want support for SoC audio on Tegra.
122 tristate "SoC Audio support for Tegra boards using an RT5640 codec"
126 Say Y or M here if you want to add support for SoC audio on Tegra
130 tristate "SoC Audio support for Tegra boards using a WM8753 codec"
134 Say Y or M here if you want to add support for SoC audio on Tegra
138 tristate "SoC Audio support for Tegra boards using a WM8903 codec"
142 Say Y or M here if you want to add support for SoC audio on Tegra
147 tristate "SoC Audio support for Tegra boards using a WM9712 codec"
152 Say Y or M here if you want to add support for SoC audio on Tegra
[all …]
/linux-5.10/drivers/thermal/tegra/
Dtegra-bpmp-thermal.c16 #include <soc/tegra/bpmp.h>
17 #include <soc/tegra/bpmp-abi.h>
20 struct tegra_bpmp_thermal *tegra; member
52 err = tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_get_temp()
79 return tegra_bpmp_transfer(zone->tegra->bpmp, &msg); in tegra_bpmp_thermal_set_trips()
96 struct tegra_bpmp_thermal *tegra = data; in bpmp_mrq_thermal() local
102 dev_err(tegra->dev, "%s: invalid request type: %d\n", in bpmp_mrq_thermal()
108 for (i = 0; i < tegra->num_zones; ++i) { in bpmp_mrq_thermal()
109 if (tegra->zones[i]->idx != req->host_trip_reached.zone) in bpmp_mrq_thermal()
112 schedule_work(&tegra->zones[i]->tz_device_update_work); in bpmp_mrq_thermal()
[all …]
DMakefile2 obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
3 obj-$(CONFIG_TEGRA_BPMP_THERMAL) += tegra-bpmp-thermal.o
5 tegra-soctherm-y := soctherm.o soctherm-fuse.o
6 tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
7 tegra-soctherm-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-soctherm.o
8 tegra-soctherm-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-soctherm.o
/linux-5.10/drivers/soc/tegra/
Dregulators-tegra20.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
33 static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, in tegra20_core_limit() argument
41 if (tegra->core_min_uV > 0) in tegra20_core_limit()
42 return tegra->core_min_uV; in tegra20_core_limit()
59 tegra->core_min_uV = core_max_uV; in tegra20_core_limit()
61 pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); in tegra20_core_limit()
63 return tegra->core_min_uV; in tegra20_core_limit()
87 static int tegra20_core_rtc_update(struct tegra_regulator_coupler *tegra, in tegra20_core_rtc_update() argument
113 core_min_uV = tegra20_core_limit(tegra, core_rdev); in tegra20_core_rtc_update()
201 static int tegra20_core_voltage_update(struct tegra_regulator_coupler *tegra, in tegra20_core_voltage_update() argument
[all …]
Dregulators-tegra30.c10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
19 #include <soc/tegra/fuse.h>
34 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, in tegra30_core_limit() argument
42 if (tegra->core_min_uV > 0) in tegra30_core_limit()
43 return tegra->core_min_uV; in tegra30_core_limit()
60 tegra->core_min_uV = core_max_uV; in tegra30_core_limit()
62 pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV); in tegra30_core_limit()
64 return tegra->core_min_uV; in tegra30_core_limit()
96 static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra, in tegra30_voltage_update() argument
142 core_min_uV = tegra30_core_limit(tegra, core_rdev); in tegra30_voltage_update()
[all …]
/linux-5.10/drivers/gpu/drm/tegra/
Ddrm.c26 #define DRIVER_NAME "tegra"
27 #define DRIVER_DESC "NVIDIA Tegra graphics"
65 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail() local
67 if (tegra->hub) { in tegra_atomic_commit_tail()
447 struct tegra_drm *tegra = drm->dev_private; in tegra_open_channel() local
459 list_for_each_entry(client, &tegra->clients, list) in tegra_open_channel()
825 struct tegra_drm *tegra = drm->dev_private; in tegra_debugfs_iova() local
828 if (tegra->domain) { in tegra_debugfs_iova()
829 mutex_lock(&tegra->mm_lock); in tegra_debugfs_iova()
830 drm_mm_print(&tegra->mm, &p); in tegra_debugfs_iova()
[all …]
Dplane.c219 struct tegra_dc_state *tegra; in tegra_plane_state_add() local
233 tegra = to_dc_state(crtc_state); in tegra_plane_state_add()
235 tegra->planes |= WIN_A_ACT_REQ << plane->index; in tegra_plane_state_add()
426 static int tegra_plane_setup_opacity(struct tegra_plane *tegra, in tegra_plane_setup_opacity() argument
453 static int tegra_plane_check_transparency(struct tegra_plane *tegra, in tegra_plane_check_transparency() argument
459 old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base); in tegra_plane_check_transparency()
467 drm_for_each_plane(plane, tegra->base.dev) { in tegra_plane_check_transparency()
471 if (p == tegra || p->dc != tegra->dc) in tegra_plane_check_transparency()
503 static void tegra_plane_update_transparency(struct tegra_plane *tegra, in tegra_plane_update_transparency() argument
515 if (p == tegra || p->dc != tegra->dc) in tegra_plane_update_transparency()
[all …]
/linux-5.10/drivers/memory/tegra/
DMakefile2 tegra-mc-y := mc.o
4 tegra-mc-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20.o
5 tegra-mc-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30.o
6 tegra-mc-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114.o
7 tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
8 tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
9 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
11 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
/linux-5.10/drivers/phy/tegra/
DMakefile2 obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
4 phy-tegra-xusb-y += xusb.o
5 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
6 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
7 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
8 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
9 phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_194_SOC) += xusb-tegra186.o
/linux-5.10/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-trimslice.txt1 NVIDIA Tegra audio complex for TrimSlice
4 - compatible : "nvidia,tegra-audio-trimslice"
7 "pll_a" (The Tegra clock of that name),
8 "pll_a_out0" (The Tegra clock of that name),
9 "mclk" (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
10 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
16 compatible = "nvidia,tegra-audio-trimslice";
Dnvidia,tegra-audio-rt5640.txt1 NVIDIA Tegra audio complex, with RT5640 CODEC
4 - compatible : "nvidia,tegra-audio-rt5640"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
22 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
25 assumes that AIF1 on the CODEC is connected to Tegra.
33 compatible = "nvidia,tegra-audio-rt5640-dalmore",
34 "nvidia,tegra-audio-rt5640";
35 nvidia,model = "NVIDIA Tegra Dalmore";
Dnvidia,tegra-audio-wm8753.txt1 NVIDIA Tegra audio complex
4 - compatible : "nvidia,tegra-audio-wm8753"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
21 - nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
26 compatible = "nvidia,tegra-audio-wm8753-whistler",
27 "nvidia,tegra-audio-wm8753"
28 nvidia,model = "tegra-wm8753-harmony";
Dnvidia,tegra-audio-rt5677.txt1 NVIDIA Tegra audio complex, with RT5677 CODEC
4 - compatible : "nvidia,tegra-audio-rt5677"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
24 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
27 assumes that AIF1 on the CODEC is connected to Tegra.
38 compatible = "nvidia,tegra-audio-rt5677-ryu",
39 "nvidia,tegra-audio-rt5677";
40 nvidia,model = "NVIDIA Tegra Ryu";
Dnvidia,tegra-audio-max98090.txt1 NVIDIA Tegra audio complex, with MAX98090 CODEC
4 - compatible : "nvidia,tegra-audio-max98090"
10 - mclk (The Tegra cdev1/extern1 clock, which feeds the CODEC's mclk)
23 - nvidia,i2s-controller : The phandle of the Tegra I2S controller that's
34 compatible = "nvidia,tegra-audio-max98090-venice2",
35 "nvidia,tegra-audio-max98090";
36 nvidia,model = "NVIDIA Tegra Venice2";
/linux-5.10/Documentation/gpu/
Dtegra.rst2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
10 Up until, but not including, Tegra124 (aka Tegra K1) the drm/tegra driver
15 The drm/tegra driver supports NVIDIA Tegra SoC generations since Tegra20. It
65 Tegra SoC generations, up until Tegra186 which introduces several changes that
71 Tegra SoCs have two display controllers, each of which can be associated with
100 The type and number of supported outputs varies between Tegra SoC generations.
116 HDMI is supported on all Tegra SoCs. Starting with Tegra210, HDMI is provided
123 Although Tegra has supported DSI since Tegra30, the controller has changed in
126 later are supported by the drm/tegra driver.
[all …]
/linux-5.10/drivers/firmware/tegra/
DMakefile2 tegra-bpmp-y = bpmp.o
3 tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
4 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
5 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
6 tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
7 obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
7 title: Tegra Power Management Controller (PMC)
34 pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
35 input to Tegra.
46 Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
48 Tegra blink pad.
51 See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
139 "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
173 match the powergates on the Tegra SoC. Each powergate node
174 represents a power-domain on the Tegra SoC that can be power-gated
[all …]
/linux-5.10/Documentation/devicetree/bindings/regulator/
Dnvidia,tegra-regulators-coupling.txt1 NVIDIA Tegra Regulators Coupling
4 NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
26 - nvidia,tegra-rtc-regulator: Boolean property that designates regulator
28 - nvidia,tegra-cpu-regulator: Boolean property that designates regulator
42 nvidia,tegra-core-regulator;
52 nvidia,tegra-rtc-regulator;
62 nvidia,tegra-cpu-regulator;

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