xref: /linux/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB I2C Controller
8
9maintainers:
10  - Jarkko Nikula <jarkko.nikula@linux.intel.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          not:
18            contains:
19              const: mscc,ocelot-i2c
20    then:
21      properties:
22        reg:
23          maxItems: 1
24
25properties:
26  compatible:
27    oneOf:
28      - description: Generic Synopsys DesignWare I2C controller
29        const: snps,designware-i2c
30      - description: Renesas RZ/N1D I2C controller
31        items:
32          - const: renesas,r9a06g032-i2c  # RZ/N1D
33          - const: renesas,rzn1-i2c       # RZ/N1
34          - const: snps,designware-i2c
35      - description: Baikal-T1 SoC System I2C controller
36        const: baikal,bt1-sys-i2c
37      - items:
38          - enum:
39              - mscc,ocelot-i2c
40              - sophgo,sg2044-i2c
41              - thead,th1520-i2c
42          - const: snps,designware-i2c
43
44  reg:
45    minItems: 1
46    items:
47      - description: DW APB I2C controller memory mapped registers
48      - description: |
49          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
50          This registers are specific to the Ocelot I2C-controller.
51
52  interrupts:
53    maxItems: 1
54
55  clocks:
56    minItems: 1
57    items:
58      - description: I2C controller reference clock source
59      - description: APB interface clock source
60
61  clock-names:
62    minItems: 1
63    items:
64      - const: ref
65      - const: pclk
66
67  resets:
68    maxItems: 1
69
70  clock-frequency:
71    description: Desired I2C bus clock frequency in Hz
72    enum: [100000, 400000, 1000000, 3400000]
73    default: 400000
74
75  i2c-sda-hold-time-ns:
76    description: |
77      The property should contain the SDA hold time in nanoseconds. This option
78      is only supported in hardware blocks version 1.11a or newer or on
79      Microsemi SoCs.
80
81  i2c-scl-falling-time-ns:
82    description: |
83      The property should contain the SCL falling time in nanoseconds.
84      This value is used to compute the tLOW period.
85    default: 300
86
87  i2c-sda-falling-time-ns:
88    description: |
89      The property should contain the SDA falling time in nanoseconds.
90      This value is used to compute the tHIGH period.
91    default: 300
92
93  dmas:
94    items:
95      - description: TX DMA Channel
96      - description: RX DMA Channel
97
98  dma-names:
99    items:
100      - const: tx
101      - const: rx
102
103  snps,bus-capacitance-pf:
104    $ref: /schemas/types.yaml#/definitions/uint32
105    description:
106      This property indicates the bus capacitance in picofarads (pF).
107      This value is used to compute the tHIGH and tLOW periods for high speed
108      mode.
109    enum: [100, 400]
110    default: 100
111
112  snps,clk-freq-optimized:
113    description:
114      This property indicates whether the hardware reduce its clock frequency
115      by reducing the internal latency required to generate the high period and
116      low period of SCL line.
117    type: boolean
118
119unevaluatedProperties: false
120
121required:
122  - compatible
123  - reg
124  - interrupts
125
126examples:
127  - |
128    i2c@f0000 {
129      compatible = "snps,designware-i2c";
130      reg = <0xf0000 0x1000>;
131      interrupts = <11>;
132      clock-frequency = <400000>;
133    };
134  - |
135    i2c@1120000 {
136      compatible = "snps,designware-i2c";
137      reg = <0x1120000 0x1000>;
138      interrupts = <12 1>;
139      clock-frequency = <400000>;
140      i2c-sda-hold-time-ns = <300>;
141      i2c-sda-falling-time-ns = <300>;
142      i2c-scl-falling-time-ns = <300>;
143      snps,bus-capacitance-pf = <400>;
144      snps,clk-freq-optimized;
145    };
146  - |
147    i2c@2000 {
148      compatible = "snps,designware-i2c";
149      reg = <0x2000 0x100>;
150      #address-cells = <1>;
151      #size-cells = <0>;
152      clock-frequency = <400000>;
153      clocks = <&i2cclk>;
154      interrupts = <0>;
155
156      eeprom@64 {
157        compatible = "atmel,24c02";
158        reg = <0x64>;
159      };
160    };
161  - |
162    i2c@100400 {
163      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
164      reg = <0x100400 0x100>, <0x198 0x8>;
165      pinctrl-0 = <&i2c_pins>;
166      pinctrl-names = "default";
167      interrupts = <8>;
168      clocks = <&ahb_clk>;
169    };
170...
171