Searched full:trm (Results 1 – 24 of 24) sorted by relevance
15 * The PL080 TRM is:17 * and the PL081 TRM is:
14 * The PL022 TRM is:
34 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
13 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
14 * It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
12 * https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
136 /* The ARM11 MPCORE TRM says the on-chip controller may have
164 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ in omap_gpio_write()
454 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data Sheet */ in pl061_enter_reset()
113 * The TRM isn't clear on behaviour if irq_clear is high when a in tz_msc_check()
15 * Documentation of it can be found in the MPS2 TRM:
22 * Links to the TRM for the board itself and to the various Application26 * Board TRM:40 * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines43 * and the AN547 uses the SSE-300, whose layout is in the SSE-300 TRM:
379 * Refer to the ug585-Zynq-7000-TRM manual B.3 (Module Summary) and in zynq_init()
22 * Links to the TRM for the board itself and to the various Application
628 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ in omap_ulpd_pm_write()685 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is in omap_ulpd_pm_write()
118 /// The TRM confusingly describes this offset as UARTRSR for reads
707 * The Neoverse-V1 r1p2 TRM lists 32-bit format CCSIDR_EL1 values, in aarch64_neoverse_v1_initfn()710 * information in chapter 2 of the TRM: in aarch64_neoverse_v1_initfn()951 * The cortex-a710 TRM does not list CCSIDR values. The layout of in aarch64_a710_initfn()1052 * The Neoverse N2 TRM does not list CCSIDR values. The layout of in aarch64_neoverse_n2_initfn()
5 * - http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
878 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format992 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
4 * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf