| /linux/Documentation/driver-api/dmaengine/ |
| H A D | provider.rst | 21 will want to start a transfer, it will assert a DMA request (DRQ) by
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
31 cycle. For example, we may want to transfer as much data as the
36 parameter called the transfer width.
44 transfer into smaller sub-transfers.
59 transfer, and whenever the transfer is started, the controller will go
73 transfer widt
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| H A D | pxa_dma.rst | 9 A driver submitting a transfer and issuing it should be granted the transfer
11 This implies that the queuing doesn't wait for the previous transfer end,
13 triggered by the end of the transfer.
14 A transfer which is submitted and issued on a phy doesn't wait for a phy to
17 a new transfer.
20 Any issued transfer with DMA_PREP_INTERRUPT should trigger a callback call.
27 multimedia case, such as video capture, if a transfer is submitted and then
28 a check of the DMA channel reports a "stopped channel", the transfer should
44 assigned on the fly when the transfer i
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| /linux/drivers/net/ethernet/qualcomm/ |
| H A D | qca_7k.c | 33 struct spi_transfer transfer[2]; in qcaspi_read_register() local
37 memset(transfer, 0, sizeof(transfer)); in qcaspi_read_register()
44 transfer[0].tx_buf = &tx_data; in qcaspi_read_register()
45 transfer[0].len = QCASPI_CMD_LEN; in qcaspi_read_register()
46 transfer[1].rx_buf = &rx_data; in qcaspi_read_register()
47 transfer[1].len = QCASPI_CMD_LEN; in qcaspi_read_register()
49 spi_message_add_tail(&transfer[0], &msg); in qcaspi_read_register()
55 spi_message_add_tail(&transfer[1], &msg); in qcaspi_read_register()
73 struct spi_transfer transfer[ in __qcaspi_write_register() local
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| /linux/drivers/mtd/devices/ |
| H A D | mchp23k256.c | 64 struct spi_transfer transfer[2] = {}; in mchp23k256_write() local
76 transfer[0].tx_buf = command; in mchp23k256_write()
77 transfer[0].len = cmd_len; in mchp23k256_write()
78 spi_message_add_tail(&transfer[0], &message); in mchp23k256_write()
80 transfer[1].tx_buf = buf; in mchp23k256_write()
81 transfer[1].len = len; in mchp23k256_write()
82 spi_message_add_tail(&transfer[1], &message); in mchp23k256_write()
103 struct spi_transfer transfer[2] = {}; in mchp23k256_read() local
112 memset(&transfer, 0, sizeof(transfer)); in mchp23k256_read()
145 struct spi_transfer transfer = {}; mchp23k256_set_mode() local
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| /linux/Documentation/mhi/ |
| H A D | mhi.rst | 58 Transfer rings: Used by the host to schedule work items for a channel. The
59 transfer rings are organized as a circular queue of Transfer Descriptors (TD).
81 Two unidirectional channels with their associated transfer rings form a
85 transfer ring.
87 Transfer rings
91 Transfer Descriptors (TD). TDs are managed through transfer rings, which are
93 memory. TDs consist of one or more ring elements (or transfer blocks)::
101 Below is the basic usage of transfer ring
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| /linux/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2x00crypto.c | 152 unsigned int transfer = 0; in rt2x00crypto_rx_insert_iv() local
194 memmove(skb->data + transfer, in rt2x00crypto_rx_insert_iv()
195 skb->data + transfer + (iv_len - align), in rt2x00crypto_rx_insert_iv()
197 transfer += header_length; in rt2x00crypto_rx_insert_iv()
203 memmove(skb->data + transfer, in rt2x00crypto_rx_insert_iv()
204 skb->data + transfer + iv_len + align, in rt2x00crypto_rx_insert_iv()
206 transfer += header_length; in rt2x00crypto_rx_insert_iv()
210 memcpy(skb->data + transfer, rxdesc->iv, iv_len); in rt2x00crypto_rx_insert_iv()
211 transfer += iv_len; in rt2x00crypto_rx_insert_iv()
218 memmove(skb->data + transfer, in rt2x00crypto_rx_insert_iv()
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| /linux/Documentation/devicetree/bindings/dma/stm32/ |
| H A D | st,stm32-dma3.yaml | 72 The third cell is a 32-bit mask specifying the DMA transfer requirements:
77 0x0: port 0 is allocated to the source transfer
78 0x1: port 1 is allocated to the source transfer
83 0x0: port 0 is allocated to the destination transfer
84 0x1: port 1 is allocated to the destination transfer
91 -bit 12-13: The transfer complete event mode
92 0x0: at block level, transfer complete event is generated at the end
94 0x2: at LLI level, the transfer complete event is generated at the end
95 of the LLI transfer
97 0x3: at channel level, the transfer complet
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| H A D | st,stm32-mdma.yaml | 24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
28 0x2: Destination address pointer is incremented after each data transfer
29 0x3: Destination address pointer is decremented after each data transfer
40 -bit 25-18: The number of bytes to be transferred in a single transfer
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
|
| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | arm,mhuv2.yaml | 33 - Data-transfer: Each transfer is made of one or more words, using one or more
36 - Doorbell: Each transfer is made up of single bit flag, using any one of the
96 The first field of a tuple signifies the transfer protocol, 0 is reserved
97 for doorbell protocol, and 1 is reserved for data-transfer protocol.
103 windows that implement the doorbell protocol. For data-transfer protocol,
105 the data-transfer protocol.
120 7 windows (separately) used in data-transfer protocol.
135 doorbell, or data-transfer protocol, and the second argument (only
144 mboxes = <&mhu 2 0>; // Channel Window Group 2, data transfer protoco
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| /linux/drivers/spi/ |
| H A D | spi-mpc52xx.c | 84 /* Details of current transfer (length, and buffer pointers) */
86 struct spi_transfer *transfer; /* current transfer */ member
113 * Start a new transfer. This is called both by the idle state
114 * for the first transfer in a message, and by the wait state when the
115 * previous transfer in a message is complete.
119 ms->rx_buf = ms->transfer->rx_buf; in mpc52xx_spi_start_transfer()
120 ms->tx_buf = ms->transfer->tx_buf; in mpc52xx_spi_start_transfer()
121 ms->len = ms->transfer->len; in mpc52xx_spi_start_transfer()
126 ms->cs_change = ms->transfer in mpc52xx_spi_start_transfer()
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| H A D | spi-cadence.c | 110 * @tx_bytes: Number of bytes left to transfer
245 * @transfer: Pointer to the spi_transfer structure which provides
246 * information about next transfer setup parameters
251 * is lower than the requested frequency (maximum lower) for the transfer. If
257 struct spi_transfer *transfer) in cdns_spi_config_clock_freq() argument
268 if (xspi->speed_hz != transfer->speed_hz) { in cdns_spi_config_clock_freq()
272 (frequency / (2 << baud_rate_val)) > transfer->speed_hz) in cdns_spi_config_clock_freq()
284 * cdns_spi_setup_transfer - Configure SPI controller for specified transfer
286 * @transfer: Pointer to the spi_transfer structure which provides
287 * information about next transfer setu
295 cdns_spi_setup_transfer(struct spi_device * spi,struct spi_transfer * transfer) cdns_spi_setup_transfer() argument
432 cdns_transfer_one(struct spi_controller * ctlr,struct spi_device * spi,struct spi_transfer * transfer) cdns_transfer_one() argument
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| H A D | spi-stm32.c | 264 * @transfer_one_dma_start: routine to start transfer a single spi_transfer
315 * @t_size_max: maximum number of data of one transfer
323 * @cur_xferlen: current transfer length in bytes
324 * @cur_usedma: boolean to know if dma is used in current transfer
329 * @dma_tx: dma channel for TX transfer
330 * @dma_rx: dma channel for RX transfer
334 * @sram_rx_buf_size: size of SRAM buffer for RX transfer
335 * @sram_rx_buf: SRAM buffer for RX transfer
336 * @sram_dma_rx_buf: SRAM buffer physical address for RX transfer
337 * @mdma_rx: MDMA channel for RX transfer
930 stm32_spi_can_dma(struct spi_controller * ctrl,struct spi_device * spi_dev,struct spi_transfer * transfer) stm32_spi_can_dma() argument
1793 stm32_spi_communication_type(struct spi_device * spi_dev,struct spi_transfer * transfer) stm32_spi_communication_type() argument
1952 stm32_spi_transfer_one_setup(struct stm32_spi * spi,struct spi_device * spi_dev,struct spi_transfer * transfer) stm32_spi_transfer_one_setup() argument
2039 stm32_spi_transfer_one(struct spi_controller * ctrl,struct spi_device * spi_dev,struct spi_transfer * transfer) stm32_spi_transfer_one() argument
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| H A D | spi-fsi.c | 299 struct spi_transfer *transfer) in fsi_spi_transfer_data() argument
306 if (transfer->tx_buf) { in fsi_spi_transfer_data()
310 const u8 *tx = transfer->tx_buf; in fsi_spi_transfer_data()
312 while (transfer->len > sent) { in fsi_spi_transfer_data()
314 (int)transfer->len - sent); in fsi_spi_transfer_data()
333 } else if (transfer->rx_buf) { in fsi_spi_transfer_data()
336 u8 *rx = transfer->rx_buf; in fsi_spi_transfer_data()
338 while (transfer->len > recv) { in fsi_spi_transfer_data()
355 (int)transfer->len - recv); in fsi_spi_transfer_data()
430 struct spi_transfer *transfer; in fsi_spi_transfer_one_message() local
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| /linux/include/linux/spi/ |
| H A D | spi.h | 64 * transfer bytes histogram
138 * The spi_transfer.speed_hz can override this for each transfer.
144 * The spi_transfer.bits_per_word can override this for each transfer.
150 * each word in a transfer (by specifying SPI_LSB_FIRST).
165 * words of a transfer
407 * supported. If set, the SPI core will reject any transfer with an
410 * @min_speed_hz: Lowest supported transfer speed
411 * @max_speed_hz: Highest supported transfer speed
416 * @max_transfer_size: function that returns the max transfer size for
433 * @transfer
681 int (*transfer)(struct spi_device *spi, global() member
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| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | colorspaces-details.rst | 14 PAL and by SDTV in general. The default transfer function is
45 The transfer function defined for SMPTE 170M is the same as the one
56 Inverse Transfer function:
92 general. The default transfer function is ``V4L2_XFER_FUNC_709``. The
121 Transfer function. Normally L is in the range [0…1], but for the
132 Inverse Transfer function:
209 and computer graphics. The default transfer function is
244 Transfer function. Note that negative values for L are only used by the
255 Inverse Transfer function:
287 graphics that use the opRGB colorspace. The default transfer functio
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| H A D | colorspaces-defs.rst | 9 which defines the chromaticities, the default transfer function, the
11 is the transfer function identifier (enum
13 transfer functions. The third is the Y'CbCr encoding identifier (enum
80 .. flat-table:: V4L2 Transfer Function
87 - Use the default transfer function as defined by the colorspace.
89 - Use the Rec. 709 transfer function.
91 - Use the sRGB transfer function.
93 - Use the opRGB transfer function.
95 - Use the SMPTE 240M transfer function.
97 - Do not use a transfer functio
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| /linux/sound/core/ |
| H A D | isadma.c | 19 * snd_dma_program - program an ISA DMA transfer
22 * @size: the DMA transfer size
23 * @mode: the DMA transfer mode, DMA_MODE_XXX
25 * Programs an ISA DMA transfer for the given buffer.
46 * snd_dma_disable - stop the ISA DMA transfer
49 * Stops the ISA DMA transfer.
63 * snd_dma_pointer - return the current pointer to DMA transfer buffer in bytes
65 * @size: the dma transfer size
67 * Return: The current pointer in DMA transfer buffer in bytes.
92 pr_err("ALSA: pointer (0x%x) for DMA #%ld is greater than transfer siz in snd_dma_pointer()
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| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 30 without the ability to generate convenient burst transfer ensuring the best
54 the STM32 DMA transfer.
58 channel is null. The channel transfer complete of the last node is the end of
59 transfer, unless first and last nodes are linked to each other, in such a
60 case, the linked-list loops on to create a circular MDMA transfer.
64 resources and bus congestion. Transfer Complete signal of STM32 DMA channel
65 can triggers STM32 MDMA transfer. STM32 MDMA can clear the request generated
73 | channels | channels | Transfer | request |
133 * the address of the STM32 DMA register to clear the Transfer Complete
135 * the mask of the Transfer Complet
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| /linux/drivers/usb/dwc2/ |
| H A D | hcd.h | 48 * @xfer_buf: Pointer to current transfer buffer position
52 * @xfer_len: Total number of bytes to transfer
54 * @start_pkt_count: Packet count at start of transfer
55 * @xfer_started: True if the transfer has been started
74 * assigned to the current transfer (not counting PINGs)
76 * @ntd: Number of transfer descriptors for the transfer
79 * @qh: QH for the transfer being processed by this channel
86 * host mode. It contains the data items needed to transfer packets to an
213 * struct dwc2_hs_transfer_time - Info about a transfer o
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| /linux/drivers/i3c/master/mipi-i3c-hci/ |
| H A D | xfer_mode_rate.h | 7 * Transfer Mode/Rate Table definitions as found in extended capability
16 * Master Transfer Mode Table Fixed Indexes.
29 * Transfer Mode Table Entry Bits Definitions
38 * Master Data Transfer Rate Selector Values.
44 * Data Transfer Rate Table. Indicated are typical rates. The actual
45 * rates may vary slightly and are also specified in the Data Transfer
67 * Master Data Transfer Rate Table Mode ID values.
73 * Master Data Transfer Rate Table Entry Bits Definitions
|
| /linux/drivers/scsi/ |
| H A D | dc395x.h | 250 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */
251 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */
273 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
319 /* transfer. */
325 /* are used to transfer data */
330 /* are used to transfer data */
333 /* 02-00 0 PERIOD[2:0]/ Synchronous SCSI Transfer Rate. */
335 /* the Synchronous SCSI Transfer */
381 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */
413 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer ou
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| /linux/arch/sh/drivers/pci/ |
| H A D | pci-sh4.h | 59 #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
60 #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
61 #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
62 #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
63 #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
80 #define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
82 #define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
84 #define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
93 #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
96 #define SH4_PCIDPA1 0x190 /* DMA1 Transfer Add
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| /linux/include/linux/ |
| H A D | atmel_pdc.h | 24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
26 #define ATMEL_PDC_RXTDIS (1 << 1) /* Receiver Transfer Disable */
27 #define ATMEL_PDC_TXTEN (1 << 8) /* Transmitter Transfer Enable */
28 #define ATMEL_PDC_TXTDIS (1 << 9) /* Transmitter Transfer Disable */
30 #define ATMEL_PDC_PTSR 0x124 /* Transfer Status Register */
|
| /linux/drivers/i2c/busses/ |
| H A D | i2c-stm32.h | 27 * @chan_tx: dma channel for TX transfer
28 * @chan_rx: dma channel for RX transfer
29 * @chan_using: dma channel used for the current transfer (TX or RX)
32 * @dma_transfer_dir: dma transfer direction indicator
33 * @dma_data_dir: dma transfer mode indicator
34 * @dma_complete: dma transfer completion
|
| /linux/Documentation/driver-api/soundwire/ |
| H A D | locking.rst | 29 SoundWire message transfer lock. This mutex is part of
38 Message transfer.
40 1. For every message transfer
44 b. Transfer message (Read/Write) to Slave1 or broadcast message on
60 | | b. Transfer message
74 2. For every message transfer in Prepare operation
78 b. Transfer message (Read/Write) to Slave1 or broadcast message on
99 | | b. Transfer message
|