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/linux-5.10/drivers/soc/qcom/
Drpmh-rsc.c25 #include <soc/qcom/tcs.h>
41 /* DRV TCS Configuration Information Register */
48 /* Offsets for common TCS Registers, one bit per TCS */
54 * Offsets for per TCS Registers.
57 * Multiply tcs_id by RSC_DRV_TCS_OFFSET to find a given TCS and add one
62 #define RSC_DRV_STATUS 0x18 /* zero if tcs is busy */
66 * Offsets for per command in a TCS.
68 * Commands (up to 16) start at 0x30 in a TCS; multiply command index
80 /* TCS CMD register bit mask */
94 * space are all the TCS blocks. The offset of the TCS blocks is
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Drpmh-internal.h12 #include <soc/qcom/tcs.h>
23 * struct tcs_group: group of Trigger Command Sets (TCS) to send state requests
27 * @type: Type of the TCS in this group - active, sleep, wake.
29 * @offset: Start of the TCS group relative to the TCSes in the RSC.
31 * @ncpt: Number of commands in each TCS.
32 * @req: Requests that are sent from the TCS; only used for ACTIVE_ONLY
33 * transfers (could be on a wake/sleep TCS if we are borrowing for
42 * MAX_CMDS_PER_TCS = 16 then bit[2] = the first bit in 2nd TCS.
94 * @tcs_base: Start address of the TCS registers in this controller.
101 * @tcs: TCS groups.
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Dtrace-rpmh.h37 TP_printk("%s: ack: tcs-m: %d addr: %#x data: %#x errno: %d",
69 TP_printk("%s: send-msg: tcs(m): %d cmd(n): %d msgid: %#x addr: %#x data: %#x complete: %d",
/linux-5.10/Documentation/devicetree/bindings/soc/qcom/
Drpmh-rsc.txt6 can be written to the Trigger Command Set (TCS) registers and using a (addr,
7 val) pair and triggered. Messages in the TCS are then sent in sequence over an
16 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
17 have powered off to facilitate idle power saving. TCS could be classified as -
45 The tcs-offset specifies the start address of the
46 TCS in the DRVs.
52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
66 - qcom,tcs-config:
69 Definition: The tuple defining the configuration of TCS.
70 Must have 2 cells which describe each TCS type.
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/linux-5.10/drivers/scsi/aic94xx/
Daic94xx_tmf.c47 #define DECLARE_TCS(tcs) \ argument
48 struct tasklet_completion_status tcs = { \
59 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_clear_nexus_tasklet_complete() local
66 tcs->dl_opcode = dl->opcode; in asd_clear_nexus_tasklet_complete()
74 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_clear_nexus_timedout() local
77 tcs->dl_opcode = TMF_RESP_FUNC_FAILED; in asd_clear_nexus_timedout()
86 DECLARE_TCS(tcs); \
95 ascb->uldd_task = &tcs; \
107 res = tcs.dl_opcode; \
248 struct tasklet_completion_status *tcs = ascb->uldd_task; in asd_tmf_timedout() local
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/linux-5.10/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c25 u8 tcs = adapter->hw_tcs; in ixgbe_cache_ring_dcb_sriov() local
28 if (tcs <= 1) in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
61 if (fcoe->offset < tcs) in ixgbe_cache_ring_dcb_sriov()
112 * TCs : TC0/1 TC2/3 TC4-7 in ixgbe_get_first_reg_idx()
125 * TCs : TC0 TC1 TC2/3 in ixgbe_get_first_reg_idx()
329 u8 tcs = adapter->hw_tcs; in ixgbe_set_dcb_sriov_queues() local
332 if (tcs <= 1) in ixgbe_set_dcb_sriov_queues()
340 vmdq_i = min_t(u16, vmdq_i, MAX_TX_QUEUES / tcs); in ixgbe_set_dcb_sriov_queues()
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Dixgbe_dcb_82599.c204 * So clear all TCs and only enable those that should be in ixgbe_dcb_config_pfc_82599()
257 /* Configure pause time (2 TCs per register) */ in ixgbe_dcb_config_pfc_82599()
295 * Tx queues are allocated non-uniformly to TCs: in ixgbe_dcb_config_tc_stats_82599()
/linux-5.10/Documentation/networking/device_drivers/ethernet/intel/
Diavf.rst155 1. Create traffic classes (TCs). Maximum of 8 TCs can be created per interface.
158 Example: Sets up two tcs, tc0 and tc1, with 16 queues each and max tx rate set
167 map: priority mapping for up to 16 priorities to tcs (e.g. map 0 0 0 0 1 1 1 1
172 number of queues for all tcs is 64 or number of cores, whichever is lower.)
176 TCs, the queue configurations, and the QoS parameters.
186 TCs are configured using mqprio.
192 3. Apply TCs to ingress (RX) flow of interface::
199 - Setting up channels via ethtool (ethtool -L) is not supported when the TCs
216 - If traffic matches multiple TC filters that point to different TCs, that
Di40e.rst664 1. Create traffic classes (TCs). Maximum of 8 TCs can be created per interface.
667 Example: Sets up two tcs, tc0 and tc1, with 16 queues each and max tx rate set
676 map: priority mapping for up to 16 priorities to tcs (e.g. map 0 0 0 0 1 1 1 1
681 number of queues for all tcs is 64 or number of cores, whichever is lower.)
685 TCs, the queue configurations, and the QoS parameters.
697 3. Apply TCs to ingress (RX) flow of interface::
705 TCs are configured using mqprio.
722 - If traffic matches multiple TC filters that point to different TCs,
/linux-5.10/Documentation/devicetree/bindings/interconnect/
Dqcom,bcm-voter.yaml24 qcom,tcs-wait:
30 The AMC TCS is triggered immediately when icc_set_bw() is called. The
63 qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/
Daq_nic.c81 if (cfg->tcs > 2) in aq_nic_cfg_update_num_vecs()
101 cfg->tcs = AQ_CFG_TCS_DEF; in aq_nic_cfg_start()
153 cfg->prio_tc_map[i] = cfg->tcs * i / 8; in aq_nic_cfg_start()
546 self->aq_vecs * cfg->tcs); in aq_nic_start()
551 self->aq_vecs * cfg->tcs); in aq_nic_start()
555 for (i = 0; i < cfg->tcs; i++) { in aq_nic_start()
918 for (tc = 0U; tc < self->aq_nic_cfg.tcs; tc++) { in aq_nic_get_stats()
1450 int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map) in aq_nic_setup_tc_mqprio() argument
1459 * disable request (tcs is 0) and we already is disabled in aq_nic_setup_tc_mqprio()
1461 if (tcs == cfg->tcs || (tcs == 0 && !cfg->is_qos)) in aq_nic_setup_tc_mqprio()
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Daq_ptp.h21 /* Index must to be 8 (8 TCs) or 16 (4 TCs).
Daq_nic.h69 u8 tcs; member
207 int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map);
Daq_filters.c175 if (fsp->ring_cookie > cfg->num_rss_queues * cfg->tcs) { in aq_check_approve_fvlan()
178 cfg->num_rss_queues * cfg->tcs - 1); in aq_check_approve_fvlan()
280 if (fsp->ring_cookie >= cfg->num_rss_queues * cfg->tcs) { in aq_rule_is_not_correct()
284 cfg->num_rss_queues * cfg->tcs - 1); in aq_rule_is_not_correct()
/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_dcb_lib.c50 * ice_dcb_get_ena_tc - return bitmap of enabled TCs
51 * @dcbcfg: DCB config to evaluate for enabled TCs
144 * ice_dcb_get_num_tc - Get the number of TCs from DCBX config
145 * @dcbcfg: config to retrieve number of TCs from
155 * enabled and create a bitmask of enabled TCs in ice_dcb_get_num_tc()
160 /* Scan bitmask for contiguous TCs starting with TC0 */ in ice_dcb_get_num_tc()
166 pr_err("Non-contiguous TCs - Disabling DCB\n"); in ice_dcb_get_num_tc()
240 /* returns number of contigous TCs and 1 TC for non-contigous TCs, in ice_dcb_bwchk()
576 * ice_dcb_tc_contig - Check that TCs are contiguous
579 * Check if TCs begin with TC0 and are contiguous
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/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
Dhw_atl2.c101 unsigned int tcs, q_per_tc; in hw_atl2_hw_queue_to_tc_map_set() local
110 tcs = 8; in hw_atl2_hw_queue_to_tc_map_set()
114 tcs = 4; in hw_atl2_hw_queue_to_tc_map_set()
121 for (tc = 0; tc != tcs; tc++) { in hw_atl2_hw_queue_to_tc_map_set()
163 tx_buff_size /= cfg->tcs; in hw_atl2_hw_qos_set()
164 rx_buff_size /= cfg->tcs; in hw_atl2_hw_qos_set()
165 for (tc = 0; tc < cfg->tcs; tc++) { in hw_atl2_hw_qos_set()
249 (BIT(nic_cfg->tcs) - 1); in hw_atl2_hw_init_tx_tc_rate_limit()
255 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl2_hw_init_tx_tc_rate_limit()
281 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl2_hw_init_tx_tc_rate_limit()
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/linux-5.10/include/soc/qcom/
Dtcs.h42 * struct tcs_request: A set of tcs_cmds sent together in a TCS
65 /* Construct a Bus Clock Manager (BCM) specific TCS command */
Drpmh.h9 #include <soc/qcom/tcs.h>
/linux-5.10/drivers/interconnect/qcom/
Dbcm-voter.c14 #include <soc/qcom/tcs.h>
30 * @tcs_wait: mask for which buckets require TCS completion
241 * qcom_icc_bcm_voter_commit - generates and commits tcs cmds based on bcms
354 if (of_property_read_u32(np, "qcom,tcs-wait", &voter->tcs_wait)) in qcom_icc_bcm_voter_probe()
Dbcm-voter.h11 #include <soc/qcom/tcs.h>
/linux-5.10/drivers/net/ethernet/intel/fm10k/
Dfm10k_dcbnl.c15 /* we support 8 TCs in all modes */ in fm10k_dcbnl_ieee_getets()
81 /* record flow control max count and state of TCs */ in fm10k_dcbnl_ieee_getpfc()
/linux-5.10/arch/mips/include/asm/
Dmips_mt.h12 * How many VPEs and TCs is Linux allowed to use? 0 means no limit.
/linux-5.10/tools/testing/selftests/drivers/net/mlxsw/
Dsharedbuffer_configuration.py78 # Multicast TCs cannot be changed
113 # Multicast TCs cannot be changed
296 # Bind each port and unicast TC (TCs < 8) to a random pool and a random
Dsch_ets.sh26 # Set the ingress quota high and use the three egress TCs to limit the
/linux-5.10/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_b0.c172 tx_buff_size /= cfg->tcs; in hw_atl_b0_hw_qos_set()
173 rx_buff_size /= cfg->tcs; in hw_atl_b0_hw_qos_set()
174 for (tc = 0; tc < cfg->tcs; tc++) { in hw_atl_b0_hw_qos_set()
353 (BIT(nic_cfg->tcs) - 1); in hw_atl_b0_hw_init_tx_tc_rate_limit()
359 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()
390 for (tc = 0; tc != nic_cfg->tcs; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()
404 (nic_cfg->tcs - num_min_rated_tcs); in hw_atl_b0_hw_init_tx_tc_rate_limit()
438 for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) { in hw_atl_b0_hw_init_tx_tc_rate_limit()

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