xref: /linux/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml (revision ab93e0dd72c37d378dd936f031ffb83ff2bd87ce) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek Power Domains Controller
8
9maintainers:
10  - MandyJH Liu <mandyjh.liu@mediatek.com>
11  - Matthias Brugger <mbrugger@suse.com>
12
13description: |
14  Mediatek processors include support for multiple power domains which can be
15  powered up/down by software based on different application scenes to save power.
16
17  IP cores belonging to a power domain should contain a 'power-domains'
18  property that is a phandle for SCPSYS node representing the domain.
19
20properties:
21  $nodename:
22    pattern: '^power-controller(@[0-9a-f]+)?$'
23
24  compatible:
25    enum:
26      - mediatek,mt6735-power-controller
27      - mediatek,mt6795-power-controller
28      - mediatek,mt6893-power-controller
29      - mediatek,mt8167-power-controller
30      - mediatek,mt8173-power-controller
31      - mediatek,mt8183-power-controller
32      - mediatek,mt8186-power-controller
33      - mediatek,mt8188-power-controller
34      - mediatek,mt8192-power-controller
35      - mediatek,mt8195-power-controller
36      - mediatek,mt8365-power-controller
37
38  '#power-domain-cells':
39    const: 1
40
41  '#address-cells':
42    const: 1
43
44  '#size-cells':
45    const: 0
46
47patternProperties:
48  "^power-domain@[0-9a-f]+$":
49    $ref: "#/$defs/power-domain-node"
50    patternProperties:
51      "^power-domain@[0-9a-f]+$":
52        $ref: "#/$defs/power-domain-node"
53        patternProperties:
54          "^power-domain@[0-9a-f]+$":
55            $ref: "#/$defs/power-domain-node"
56            patternProperties:
57              "^power-domain@[0-9a-f]+$":
58                $ref: "#/$defs/power-domain-node"
59                patternProperties:
60                  "^power-domain@[0-9a-f]+$":
61                    $ref: "#/$defs/power-domain-node"
62                    unevaluatedProperties: false
63                unevaluatedProperties: false
64            unevaluatedProperties: false
65        unevaluatedProperties: false
66    unevaluatedProperties: false
67
68$defs:
69  power-domain-node:
70    type: object
71    description: |
72      Represents the power domains within the power controller node as documented
73      in Documentation/devicetree/bindings/power/power-domain.yaml.
74
75    properties:
76
77      '#power-domain-cells':
78        description:
79          Must be 0 for nodes representing a single PM domain and 1 for nodes
80          providing multiple PM domains.
81
82      '#address-cells':
83        const: 1
84
85      '#size-cells':
86        const: 0
87
88      reg:
89        description: |
90          Power domain index. Valid values are defined in:
91              "include/dt-bindings/power/mt6795-power.h" - for MT8167 type power domain.
92              "include/dt-bindings/power/mediatek,mt6893-power.h" - for MT6893 type power domain.
93              "include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
94              "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
95              "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
96              "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
97              "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
98              "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
99              "include/dt-bindings/power/mediatek,mt8365-power.h" - for MT8365 type power domain.
100        maxItems: 1
101
102      clocks:
103        description: |
104          A number of phandles to clocks that need to be enabled during domain
105          power-up sequencing.
106
107      clock-names:
108        description: |
109          List of names of clocks, in order to match the power-up sequencing
110          for each power domain we need to group the clocks by name. BASIC
111          clocks need to be enabled before enabling the corresponding power
112          domain, and should not have a '-' in their name (i.e mm, mfg, venc).
113          SUSBYS clocks need to be enabled before releasing the bus protection,
114          and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
115
116          In order to follow properly the power-up sequencing, the clocks must
117          be specified by order, adding first the BASIC clocks followed by the
118          SUSBSYS clocks.
119
120      domain-supply:
121        description: domain regulator supply.
122
123      mediatek,infracfg:
124        $ref: /schemas/types.yaml#/definitions/phandle
125        description: phandle to the device containing the INFRACFG register range.
126
127      mediatek,infracfg-nao:
128        $ref: /schemas/types.yaml#/definitions/phandle
129        description: phandle to the device containing the INFRACFG-NAO register range.
130
131      mediatek,smi:
132        $ref: /schemas/types.yaml#/definitions/phandle
133        description: phandle to the device containing the SMI register range.
134
135    required:
136      - reg
137
138required:
139  - compatible
140
141additionalProperties: false
142
143examples:
144  - |
145    #include <dt-bindings/clock/mt8173-clk.h>
146    #include <dt-bindings/power/mt8173-power.h>
147
148    soc {
149        #address-cells = <2>;
150        #size-cells = <2>;
151
152        scpsys: syscon@10006000 {
153            compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
154            reg = <0 0x10006000 0 0x1000>;
155
156            spm: power-controller {
157                compatible = "mediatek,mt8173-power-controller";
158                #address-cells = <1>;
159                #size-cells = <0>;
160                #power-domain-cells = <1>;
161
162                /* power domains of the SoC */
163                power-domain@MT8173_POWER_DOMAIN_VDEC {
164                    reg = <MT8173_POWER_DOMAIN_VDEC>;
165                    clocks = <&topckgen CLK_TOP_MM_SEL>;
166                    clock-names = "mm";
167                    #power-domain-cells = <0>;
168                };
169                power-domain@MT8173_POWER_DOMAIN_VENC {
170                    reg = <MT8173_POWER_DOMAIN_VENC>;
171                    clocks = <&topckgen CLK_TOP_MM_SEL>,
172                             <&topckgen CLK_TOP_VENC_SEL>;
173                    clock-names = "mm", "venc";
174                    #power-domain-cells = <0>;
175                };
176                power-domain@MT8173_POWER_DOMAIN_ISP {
177                    reg = <MT8173_POWER_DOMAIN_ISP>;
178                    clocks = <&topckgen CLK_TOP_MM_SEL>;
179                    clock-names = "mm";
180                    #power-domain-cells = <0>;
181                };
182                power-domain@MT8173_POWER_DOMAIN_MM {
183                    reg = <MT8173_POWER_DOMAIN_MM>;
184                    clocks = <&topckgen CLK_TOP_MM_SEL>;
185                    clock-names = "mm";
186                    #power-domain-cells = <0>;
187                    mediatek,infracfg = <&infracfg>;
188                };
189                power-domain@MT8173_POWER_DOMAIN_VENC_LT {
190                    reg = <MT8173_POWER_DOMAIN_VENC_LT>;
191                    clocks = <&topckgen CLK_TOP_MM_SEL>,
192                             <&topckgen CLK_TOP_VENC_LT_SEL>;
193                    clock-names = "mm", "venclt";
194                    #power-domain-cells = <0>;
195                };
196                power-domain@MT8173_POWER_DOMAIN_AUDIO {
197                    reg = <MT8173_POWER_DOMAIN_AUDIO>;
198                    #power-domain-cells = <0>;
199                };
200                power-domain@MT8173_POWER_DOMAIN_USB {
201                    reg = <MT8173_POWER_DOMAIN_USB>;
202                    #power-domain-cells = <0>;
203                };
204                power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
205                    reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
206                    clocks = <&clk26m>;
207                    clock-names = "mfg";
208                    #address-cells = <1>;
209                    #size-cells = <0>;
210                    #power-domain-cells = <1>;
211
212                    power-domain@MT8173_POWER_DOMAIN_MFG_2D {
213                        reg = <MT8173_POWER_DOMAIN_MFG_2D>;
214                        #address-cells = <1>;
215                        #size-cells = <0>;
216                        #power-domain-cells = <1>;
217
218                        power-domain@MT8173_POWER_DOMAIN_MFG {
219                            reg = <MT8173_POWER_DOMAIN_MFG>;
220                            #power-domain-cells = <0>;
221                            mediatek,infracfg = <&infracfg>;
222                        };
223                    };
224                };
225            };
226        };
227    };
228