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/linux-6.8/Documentation/devicetree/bindings/interconnect/
Dqcom,sm8650-rpmh.yaml4 $id: http://devicetree.org/schemas/interconnect/qcom,sm8650-rpmh.yaml#
7 title: Qualcomm RPMh Network-On-Chip Interconnect on SM8650
21 See also:: include/dt-bindings/interconnect/qcom,sm8650-rpmh.h
26 - qcom,sm8650-aggre1-noc
27 - qcom,sm8650-aggre2-noc
28 - qcom,sm8650-clk-virt
29 - qcom,sm8650-cnoc-main
30 - qcom,sm8650-config-noc
31 - qcom,sm8650-gem-noc
32 - qcom,sm8650-lpass-ag-noc
[all …]
Dqcom,msm8998-bwmon.yaml37 - qcom,sm8650-cpu-bwmon
46 - qcom,sm8650-llcc-bwmon
/linux-6.8/Documentation/devicetree/bindings/display/msm/
Dqcom,sm8650-mdss.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
7 title: Qualcomm SM8650 Display MDSS
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
20 const: qcom,sm8650-mdss
42 const: qcom,sm8650-dpu
48 const: qcom,sm8650-dp
55 - const: qcom,sm8650-dsi-ctrl
62 const: qcom,sm8650-dsi-phy-4nm
76 compatible = "qcom,sm8650-mdss";
100 compatible = "qcom,sm8650-dpu";
[all …]
Dqcom,sm8650-dpu.yaml4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-dpu.yaml#
7 title: Qualcomm SM8650 Display DPU
16 const: qcom,sm8650-dpu
59 compatible = "qcom,sm8650-dpu";
/linux-6.8/Documentation/devicetree/bindings/pinctrl/
Dqcom,sm8650-lpass-lpi-pinctrl.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml#
7 title: Qualcomm SM8650 SoC LPASS LPI TLMM
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC.
19 const: qcom,sm8650-lpass-lpi-pinctrl
38 - $ref: "#/$defs/qcom-sm8650-lpass-state"
41 $ref: "#/$defs/qcom-sm8650-lpass-state"
45 qcom-sm8650-lpass-state:
90 compatible = "qcom,sm8650-lpass-lpi-pinctrl";
Dqcom,sm8650-tlmm.yaml4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml#
7 title: Qualcomm Technologies, Inc. SM8650 TLMM block
13 Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC.
20 const: qcom,sm8650-tlmm
38 - $ref: "#/$defs/qcom-sm8650-tlmm-state"
41 $ref: "#/$defs/qcom-sm8650-tlmm-state"
45 qcom-sm8650-tlmm-state:
113 compatible = "qcom,sm8650-tlmm";
/linux-6.8/Documentation/devicetree/bindings/clock/
Dqcom,sm8650-gcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#
7 title: Qualcomm Global Clock & Reset Controller on SM8650
14 domains on SM8650
16 See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h
20 const: qcom,sm8650-gcc
48 compatible = "qcom,sm8650-gcc";
Dqcom,sm8650-dispcc.yaml4 $id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8650
15 domains on SM8650.
17 See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
22 - qcom,sm8650-dispcc
77 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
82 compatible = "qcom,sm8650-dispcc";
Dqcom,sm8550-tcsr.yaml18 - include/dt-bindings/clock/qcom,sm8650-tcsr.h
25 - qcom,sm8650-tcsr
Dqcom,sm8450-gpucc.yaml20 include/dt-bindings/reset/qcom,sm8650-gpucc.h
27 - qcom,sm8650-gpucc
/linux-6.8/arch/arm64/boot/dts/qcom/
Dsm8650-qrd.dts10 #include "sm8650.dtsi"
21 model = "Qualcomm Technologies, Inc. SM8650 QRD";
22 compatible = "qcom,sm8650-qrd", "qcom,sm8650";
50 compatible = "qcom,sm8650-pmic-glink",
452 firmware-name = "qcom/sm8650/ipa_fws.mbn";
612 firmware-name = "qcom/sm8650/adsp.mbn",
613 "qcom/sm8650/adsp_dtb.mbn";
619 firmware-name = "qcom/sm8650/cdsp.mbn",
620 "qcom/sm8650/cdsp_dtb.mbn";
626 firmware-name = "qcom/sm8650/modem.mbn",
[all …]
Dsm8650-mtp.dts9 #include "sm8650.dtsi"
20 model = "Qualcomm Technologies, Inc. SM8650 MTP";
21 compatible = "qcom,sm8650-mtp", "qcom,sm8650";
32 compatible = "qcom,sm8650-pmic-glink",
553 firmware-name = "qcom/sm8650/adsp.mbn",
554 "qcom/sm8650/adsp_dtb.mbn";
560 firmware-name = "qcom/sm8650/cdsp.mbn",
561 "qcom/sm8650/cdsp_dtb.mbn";
567 firmware-name = "qcom/sm8650/modem.mbn",
568 "qcom/sm8650/modem_dtb.mbn";
Dsm8650.dtsi7 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
10 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
15 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
21 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
373 compatible = "qcom,scm-sm8650", "qcom,scm";
380 compatible = "qcom,sm8650-clk-virt";
386 compatible = "qcom,sm8650-mc-virt";
749 compatible = "qcom,sm8650-gcc";
[all …]
/linux-6.8/drivers/clk/qcom/
Dtcsrcc-sm8650.c14 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
151 { .compatible = "qcom,sm8650-tcsr" },
164 .name = "tcsr_cc-sm8650",
181 MODULE_DESCRIPTION("QTI TCSRCC SM8650 Driver");
DMakefile116 obj-$(CONFIG_SM_DISPCC_8650) += dispcc-sm8650.o
128 obj-$(CONFIG_SM_GCC_8650) += gcc-sm8650.o
138 obj-$(CONFIG_SM_GPUCC_8650) += gpucc-sm8650.o
140 obj-$(CONFIG_SM_TCSRCC_8650) += tcsrcc-sm8650.o
Dgpucc-sm8650.c13 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
14 #include <dt-bindings/reset/qcom,sm8650-gpucc.h>
634 { .compatible = "qcom,sm8650-gpucc" },
656 .name = "sm8650-gpucc",
662 MODULE_DESCRIPTION("QTI GPU_CC SM8650 Driver");
DKconfig875 tristate "SM8650 Display Clock Controller"
880 SM8650 devices.
981 tristate "SM8650 Global Clock Controller"
985 Support for the global clock controller on SM8650 devices.
1071 tristate "SM8650 Graphics Clock Controller"
1074 Support for the graphics clock controller on SM8650 devices.
1087 tristate "SM8650 TCSR Clock Controller"
1091 Support for the TCSR clock controller on SM8650 devices.
/linux-6.8/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-pcie-phy.yaml39 - qcom,sm8650-qmp-gen3x2-pcie-phy
40 - qcom,sm8650-qmp-gen4x2-pcie-phy
152 - qcom,sm8650-qmp-gen3x2-pcie-phy
153 - qcom,sm8650-qmp-gen4x2-pcie-phy
196 - qcom,sm8650-qmp-gen4x2-pcie-phy
Dqcom,sc8280xp-qmp-ufs-phy.yaml35 - qcom,sm8650-qmp-ufs-phy
116 - qcom,sm8650-qmp-ufs-phy
Dqcom,sc8280xp-qmp-usb43dp-phy.yaml30 - qcom,sm8650-qmp-usb3-dp-phy
133 - qcom,sm8650-qmp-usb3-dp-phy
/linux-6.8/drivers/interconnect/qcom/
Dsm8650.c13 #include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
18 #include "sm8650.h"
1633 { .compatible = "qcom,sm8650-aggre1-noc", .data = &sm8650_aggre1_noc },
1634 { .compatible = "qcom,sm8650-aggre2-noc", .data = &sm8650_aggre2_noc },
1635 { .compatible = "qcom,sm8650-clk-virt", .data = &sm8650_clk_virt },
1636 { .compatible = "qcom,sm8650-config-noc", .data = &sm8650_config_noc },
1637 { .compatible = "qcom,sm8650-cnoc-main", .data = &sm8650_cnoc_main },
1638 { .compatible = "qcom,sm8650-gem-noc", .data = &sm8650_gem_noc },
1639 { .compatible = "qcom,sm8650-lpass-ag-noc", .data = &sm8650_lpass_ag_noc },
1640 { .compatible = "qcom,sm8650-lpass-lpiaon-noc", .data = &sm8650_lpass_lpiaon_noc },
[all …]
DMakefile34 qnoc-sm8650-objs := sm8650.o
66 obj-$(CONFIG_INTERCONNECT_QCOM_SM8650) += qnoc-sm8650.o
/linux-6.8/drivers/pinctrl/qcom/
Dpinctrl-sm8650-lpass-lpi.c213 .compatible = "qcom,sm8650-lpass-lpi-pinctrl",
222 .name = "qcom-sm8650-lpass-lpi-pinctrl",
230 MODULE_DESCRIPTION("Qualcomm SM8650 LPI GPIO pin control driver");
DMakefile62 obj-$(CONFIG_PINCTRL_SM8650) += pinctrl-sm8650.o
63 obj-$(CONFIG_PINCTRL_SM8650_LPASS_LPI) += pinctrl-sm8650-lpass-lpi.o
/linux-6.8/Documentation/devicetree/bindings/firmware/
Dqcom,scm.yaml66 - qcom,scm-sm8650
192 - qcom,scm-sm8650

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