| /linux-5.10/arch/arm/mach-zynq/ |
| D | slcr.c | 3 * Xilinx SLCR driver
34 * zynq_slcr_write - Write to a register in SLCR block
37 * @offset: Register offset in SLCR block
47 * zynq_slcr_read - Read a register in SLCR block
49 * @val: Pointer to value to be read from SLCR
50 * @offset: Register offset in SLCR block
60 * zynq_slcr_unlock - Unlock SLCR registers
189 * zynq_early_slcr_init - Early slcr init function
193 * Called very early during boot from platform code to unlock SLCR.
199 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); in zynq_early_slcr_init()
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| D | Makefile | 7 obj-y := common.o slcr.o pm.o
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| D | platsmp.c | 36 /* MS: Expectation that SLCR are directly map and accessible */ in zynq_cpun_start()
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| /linux-5.10/drivers/reset/ |
| D | reset-zynq.c | 21 struct regmap *slcr; member
40 return regmap_update_bits(priv->slcr, in zynq_reset_assert()
57 return regmap_update_bits(priv->slcr, in zynq_reset_deassert()
76 ret = regmap_read(priv->slcr, priv->offset + (bank * 4), ®); in zynq_reset_status()
99 priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in zynq_reset_probe()
101 if (IS_ERR(priv->slcr)) { in zynq_reset_probe()
102 dev_err(&pdev->dev, "unable to get zynq-slcr regmap"); in zynq_reset_probe()
103 return PTR_ERR(priv->slcr); in zynq_reset_probe()
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| /linux-5.10/Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 9 - reg: SLCR offset and size taken via syscon <0x200 0x48>
10 - syscon: <&slcr>
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
21 syscon = <&slcr>;
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| /linux-5.10/drivers/fpga/ |
| D | zynq-fpga.c | 27 /* Offsets into SLCR regmap */
110 /* Masks for controlling stuff in SLCR */
127 struct regmap *slcr; member
286 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_init()
290 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
293 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_init()
513 regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET, in zynq_fpga_ops_write_complete()
517 regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET, in zynq_fpga_ops_write_complete()
571 priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node, in zynq_fpga_probe()
573 if (IS_ERR(priv->slcr)) { in zynq_fpga_probe()
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| /linux-5.10/Documentation/devicetree/bindings/fpga/ |
| D | xilinx-zynq-fpga-mgr.txt | 9 - syscon: phandle for access to SLCR registers
18 syscon = <&slcr>;
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| D | fpga-region.txt | 362 syscon = <&slcr>;
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| /linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | xlnx,zynq-pinctrl.txt | 5 - syscon: phandle to SLCR
6 - reg: Offset and length of pinctrl space in SLCR
81 syscon = <&slcr>;
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| /linux-5.10/arch/arm/boot/dts/ |
| D | zynq-7000.dtsi | 275 slcr: slcr@f8000000 { label
278 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
303 syscon = <&slcr>;
309 syscon = <&slcr>;
338 syscon = <&slcr>;
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| /linux-5.10/drivers/clk/zynq/ |
| D | clkc.c | 584 struct device_node *slcr; in zynq_clock_init() local
598 slcr = of_get_parent(np); in zynq_clock_init()
600 if (slcr->data) { in zynq_clock_init()
601 zynq_clkc_base = (__force void __iomem *)slcr->data + res.start; in zynq_clock_init()
604 of_node_put(slcr); in zynq_clock_init()
610 of_node_put(slcr); in zynq_clock_init()
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| /linux-5.10/Documentation/devicetree/bindings/soc/xilinx/ |
| D | xlnx,vcu.txt | 16 1. vcu slcr
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| /linux-5.10/drivers/pci/controller/ |
| D | pcie-xilinx-cpm.c | 104 * @cpm_base: CPM System Level Control and Status Register(SLCR) Base
290 * CPM SLCR block. in xilinx_cpm_pcie_event_flow()
482 * CPM SLCR block. in xilinx_cpm_pcie_init_port()
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | zynq-7000.txt | 17 - reg : SLCR offset and size taken via syscon < 0x100 0x100 >
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| /linux-5.10/drivers/soc/xilinx/ |
| D | xlnx_vcu.c | 47 /* vcu slcr registers, bitmask and shift */
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| /linux-5.10/drivers/net/ethernet/mellanox/mlxsw/ |
| D | reg.h | 1339 /* SLCR - Switch LAG Configuration 2 Register
1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
1452 MLXSW_REG_ZERO(slcr, payload); in mlxsw_reg_slcr_pack()
11126 MLXSW_REG(slcr),
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| D | spectrum.c | 2434 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl); in mlxsw_sp_lag_init()
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