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Searched full:sgis (Results 1 – 19 of 19) sorted by relevance

/linux-5.10/include/kvm/
Darm_vgic.h97 struct kvm_vcpu *vcpu; /* SGIs and PPIs: The VCPU
123 u8 source; /* GICv2 SGIs only */
124 u8 active_source; /* GICv2 SGIs only */
234 /* Wants SGIs without active state */
/linux-5.10/arch/arm64/kvm/vgic/
Dvgic-mmio-v3.c121 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_write_v3_misc()
131 /* Switching HW SGIs? */ in vgic_mmio_write_v3_misc()
166 /* Not a GICv4.1? No HW SGIs */ in vgic_mmio_uaccess_write_v3_misc()
522 * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
961 * @allow_group1: Does the sysreg access allow generation of G1 SGIs
963 * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
1022 * An access targeting Group0 SGIs can only generate in vgic_v3_dispatch_sgi()
1023 * those, while an access targeting Group1 SGIs can in vgic_v3_dispatch_sgi()
Dvgic.c93 /* SGIs and PPIs */ in vgic_get_irq()
595 /* SGIs and LPIs cannot be wired up to any device */ in kvm_vgic_set_owner()
771 /* GICv2 SGIs can count for more than one... */ in compute_ap_list_depth()
803 * If we have multi-SGIs in the pipeline, we need to in vgic_flush_lr_state()
Dvgic-init.c199 * Enable and configure all SGIs to be edge-triggered and in kvm_vgic_vcpu_init()
212 /* SGIs */ in kvm_vgic_vcpu_init()
Dvgic-mmio.c327 * GICv2 SGIs are terribly broken. We can't restore in vgic_uaccess_write_spending()
419 * More fun with GICv2 SGIs! If we're clearing one of them in vgic_uaccess_write_cpending()
723 * The configuration cannot be changed for SGIs in general, in vgic_mmio_write_config()
Dvgic-kvm-device.c182 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs in vgic_set_common_attr()
/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Darm,gic.yaml17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
19 have PPIs or SGIs.
Dti,omap4-wugen-mpu20 - Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
Dnvidia,tegra20-ictlr.txt27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
/linux-5.10/drivers/irqchip/
Dirq-hip04.c122 /* Interrupt configuration for SGIs can't be changed */ in hip04_irq_set_type()
333 /* Get the interrupt number and add 16 to skip over SGIs */ in hip04_irq_domain_xlate()
Dirq-gic-common.c119 * Deactivate and disable all SPIs. Leave the PPI and SGIs in gic_dist_config()
Dirq-gic.c297 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
365 * works because we don't nest SGIs... in gic_handle_irq()
949 * Now let's migrate and clear any potential SGIs that might be in gic_migrate_target()
956 * for previously sent SGIs by us to other CPUs either. in gic_migrate_target()
1188 * For primary GICs, skip over SGIs. in gic_init_bases()
Dirq-alpine-msi.c35 u32 num_spis; /* The number of SGIs for MSIs */
Dirq-gic-v3.c558 /* Interrupt configuration for SGIs can't be changed */ in gic_set_type()
755 pr_info("Enabling SGIs without active state\n"); in gic_dist_init()
1001 /* Check all the CPUs have capable of sending SGIs to other CPUs */ in gic_cpu_sys_reg_init()
1056 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1164 /* Register all 8 non-secure SGIs */ in gic_smp_init()
Dirq-gic-v3-its.c4189 * There is no notion of affinity for virtual SGIs, at least in its_sgi_set_affinity()
4306 /* Yes, we do want 16 SGIs */ in its_sgi_irq_domain_alloc()
/linux-5.10/drivers/gpio/
Dgpio-xgene-sb.c195 /* Skip SGIs and PPIs*/ in xgene_gpio_sb_domain_alloc()
/linux-5.10/Documentation/virt/kvm/devices/
Darm-vgic-v3.rst273 SGIs and any interrupt with a higher ID than the number of interrupts
/linux-5.10/arch/arm/common/
DbL_switcher.c215 /* redirect GIC's SGIs to our counterpart */ in bL_switch_to()
/linux-5.10/arch/arm64/kvm/
Dsys_regs.c283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, in access_gic_sgi()