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/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c8 * 7 - SDRAM auto-power-up failure (rev A0)
10 * SDRAM reads (rev A0, B0, B1)
14 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
144 struct sdram_params *sdram) in sdram_calculate_timing() argument
152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
158 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
167 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
173 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
174 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,sdram-props.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
7 title: Common properties for SDRAM types
10 Different SDRAM types generally use the same properties and only differ in the
13 a SDRAM channel node.
25 For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
26 For LPDDR SDRAM:
29 For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
34 The former form is useful when the SDRAM vendor and part number are
36 form is useful when SDRAM nodes are created at runtime by boot firmware
49 SDRAM revision ID:
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H A Djedec,sdram-channel.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
7 title: SDRAM channel with chip/rank topology description
10 A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
21 pattern: "sdram-channel-[0-9]+$"
34 from (a multiple of) the io-width of the SDRAM chip, that means that
40 connected SDRAM chip, times the io-width of the channel divided by
41 the io-width of the SDRAM chip.
59 Each physical SDRAM chip may have one or more ranks. Ranks are
60 internal but fully independent sub-units of the chip. Each SDRAM bus
124 sdram-channel-0 {
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/linux/drivers/edac/
H A Daltera_edac.h14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
48 /* SDRAM Controller DRAM Status Register Bit Masks */
53 /* SDRAM Controller DRAM IRQ Register */
56 /* SDRAM Controlle
[all...]
/linux/arch/arm/mach-pxa/
H A Dsmemc.h15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
52 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
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H A Dsleep.S55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
160 @ external accesses after SDRAM is put in self-refresh mode
166 @ put SDRAM into self-refresh
/linux/include/soc/at91/
H A Dat91sam9_sdramc.h8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
15 /* SDRAM Controller (SDRAMC) registers */
16 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
29 #define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
56 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
70 #define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
71 #define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
72 #define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
73 #define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
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H A Dsama7-ddr.h55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 #define UDDRC_STAT_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused so…
58 #define UDDRC_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by A…
/linux/Documentation/devicetree/bindings/edac/
H A Daspeed,ast2400-sdram-edac.yaml4 $id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml#
7 title: Aspeed BMC SoC SDRAM EDAC controller
25 - aspeed,ast2400-sdram-edac
26 - aspeed,ast2500-sdram-edac
27 - aspeed,ast2600-sdram-edac
44 sdram@1e6e0000 {
45 compatible = "aspeed,ast2500-sdram-edac";
H A Daltr,socfpga-ecc-manager.yaml56 - altr,sdram-edac
57 - altr,sdram-edac-a10
58 - altr,sdram-edac-s10
66 description: phandle to SDRAM parent
279 compatible = "altr,sdram-edac-s10";
/linux/drivers/net/usb/
H A Dsr9700.h108 /* Tx sdram Write Pointer Address Low */
110 /* Tx sdram Write Pointer Address High */
112 /* Tx sdram Read Pointer Address Low */
114 /* Tx sdram Read Pointer Address High */
116 /* Rx sdram Write Pointer Address Low */
118 /* Rx sdram Write Pointer Address High */
120 /* Rx sdram Read Pointer Address Low */
122 /* Rx sdram Read Pointer Address High */
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80-de.c42 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
44 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
46 static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
48 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
50 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
52 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
54 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
56 static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
58 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
60 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmarvell,mvebu-sdram-controller.yaml4 $id: http://devicetree.org/schemas/memory-controllers/marvell,mvebu-sdram-controller.yaml#
7 title: Marvell MVEBU SDRAM controller
15 const: marvell,armada-xp-sdram-controller
29 compatible = "marvell,armada-xp-sdram-controller";
/linux/drivers/fpga/
H A Daltera-fpga2sdram.c3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
13 * Reconfiguring these ports requires that no SDRAM transactions occur during
14 * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
164 MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
/linux/arch/m68k/include/asm/
H A Dm520xsim.h74 * SDRAM configuration registers.
76 #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
77 #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
78 #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
79 #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
80 #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
81 #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
/linux/drivers/clk/pxa/
H A Dclk-pxa.c23 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
24 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
25 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
26 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
27 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
169 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock in pxa2xx_cpll_change()
182 /* If we're dividing the memory clock by two for the SDRAM clock, this in pxa2xx_cpll_change()
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dralink,rt2880-pinctrl.yaml38 enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
57 enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
107 const: sdram
111 enum: [sdram]
H A Dralink,rt305x-pinctrl.yaml39 pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf,
59 enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite]
154 const: sdram
158 enum: [sdram]
/linux/arch/m68k/coldfire/
H A Dm53xx.c61 DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
99 CLKDEV_INIT("sdram.0", NULL, &__clk_0_46),
122 &__clk_0_46, /* sdram.0 */
268 * SDRAM Timing Parameters
369 * Check to see if the SDRAM has already been initialized in sdramc_init()
373 /* SDRAM chip select initialization */ in sdramc_init()
375 /* Initialize SDRAM chip select */ in sdramc_init()
501 * Check to see if the SDRAM has already been initialized. in clock_pll()
502 * If it has then the SDRAM needs to be put into self refresh in clock_pll()
506 /* Put SDRAM into self refresh mode */ in clock_pll()
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/linux/arch/sh/drivers/pci/
H A Dpci-sh7751.c25 /* check BCR for SDRAM in area */ in __area_sdram_check()
27 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n", in __area_sdram_check()
34 /* check BCR2 for 32bit SDRAM interface*/ in __area_sdram_check()
36 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n", in __area_sdram_check()
141 /* check BCR for SDRAM in specified area */ in sh7751_pci_init()
/linux/arch/powerpc/platforms/52xx/
H A Dmpc52xx_sleep.S10 mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
68 /* put SDRAM into self-refresh */
69 lwz r8, 0x4(r4) /* sdram->ctrl */
89 /* disable SDRAM clock */
/linux/arch/arm/mach-lpc32xx/
H A Dpm.c40 * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
126 * Setup SDRAM self-refresh clock to automatically disable o in lpc32xx_pm_init()
/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux/arch/arm/mach-imx/
H A Dmx3x.h21 * 80000000 256M CSD0 SDRAM/DDR
22 * 90000000 256M CSD1 SDRAM/DDR
29 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
127 * NAND, SDRAM, WEIM, M3IF, EMI controllers

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