Searched full:sdr12 (Results 1 – 25 of 70) sorted by relevance
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| /linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-am654.yaml | 69 ti,otap-del-sel-sdr12:
70 description: Output tap delay for SD UHS SDR12 timing
139 ti,itap-del-sel-sdr12:
140 description: Input tap delay for SD UHS SDR12 timing
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| D | cdns,sdhci.yaml | 49 cdns,phy-input-delay-sd-uhs-sdr12:
50 description: Value of the delay in the input path for SD UHS SDR12 timing
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| D | sdhci-omap.txt | 14 - pinctrl-names: Should be subset of "default", "hs", "sdr12", "sdr25", "sdr50",
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| D | socionext,uniphier-sd.yaml | 98 sd-uhs-sdr12;
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| D | k3-dw-mshc.txt | 59 sd-uhs-sdr12;
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| D | mmc-controller.yaml | 131 sd-uhs-sdr12:
134 SD UHS SDR12 speed is supported.
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| D | marvell,xenon-sdhci.txt | 84 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
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| /linux-5.10/arch/arm/boot/dts/ |
| D | imx6qdl-colibri-v1_1-uhs.dtsi | 40 sd-uhs-sdr12;
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| D | rk3288-veyron-sdmmc.dtsi | 83 sd-uhs-sdr12;
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| D | dra7-evm.dts | 389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
420 …pinctrl-names = "default-rev11", "default", "hs-rev11", "hs", "sdr12-rev11", "sdr12", "sdr25-rev11…
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| D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| D | imx6ull-colibri-eval-v3.dtsi | 173 sd-uhs-sdr12;
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| D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| D | rk3288-phycore-rdk.dts | 231 sd-uhs-sdr12;
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| D | ste-href.dtsi | 138 sd-uhs-sdr12;
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| /linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a-clearfog-itx.dtsi | 31 sd-uhs-sdr12;
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| D | fsl-ls1012a-rdb.dts | 25 sd-uhs-sdr12;
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| D | fsl-lx2160a-rdb.dts | 70 sd-uhs-sdr12;
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| D | fsl-ls1046a-rdb.dts | 43 sd-uhs-sdr12;
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| D | fsl-ls1028a-rdb.dts | 90 sd-uhs-sdr12;
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| /linux-5.10/drivers/mmc/host/ |
| D | sdhci-acpi.c | 669 * a) The clock divisor for SDR12, SDR25, and SDR50 is too small. in sdhci_acpi_emmc_amd_probe_slot()
671 * acceptable. i.e., SDR12 = 25 MHz, SDR25 = 50 MHz, SDR50 = in sdhci_acpi_emmc_amd_probe_slot()
681 * These presets have proper clock divisors. i.e., SDR12 => 12MHz, in sdhci_acpi_emmc_amd_probe_slot()
698 * firmware that that has valid presets (i.e., SDR12 <= 12 MHz). in sdhci_acpi_emmc_amd_probe_slot()
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| D | dw_mmc-k3.c | 80 {6, 0, 15, 15,}, /* 3: SDR12 */
92 {6, 0, 15, 15,}, /* 3: SDR12 */
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| /linux-5.10/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxbb-p20x.dtsi | 196 sd-uhs-sdr12;
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| /linux-5.10/drivers/mmc/core/ |
| D | debugfs.c | 129 str = "sd uhs SDR12"; in mmc_ios_show()
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| /linux-5.10/arch/arm64/boot/dts/rockchip/ |
| D | rk3368-px5-evb.dts | 243 sd-uhs-sdr12;
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