xref: /src/sys/contrib/device-tree/Bindings/mmc/wm,wm8505-sdhc.yaml (revision ae5de77ed78ae54d86cead5604869212e8008e6b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/wm,wm8505-sdhc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: WonderMedia SoC SDHCI Controller
8
9maintainers:
10  - Alexey Charkov <alchark@gmail.com>
11
12allOf:
13  - $ref: mmc-controller.yaml#
14
15properties:
16  compatible:
17    oneOf:
18      - const: wm,wm8505-sdhc
19      - items:
20          - const: wm,wm8650-sdhc
21          - const: wm,wm8505-sdhc
22      - items:
23          - const: wm,wm8750-sdhc
24          - const: wm,wm8505-sdhc
25      - items:
26          - const: wm,wm8850-sdhc
27          - const: wm,wm8505-sdhc
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    maxItems: 1
34
35  interrupts:
36    items:
37      - description: SDMMC controller interrupt
38      - description: SDMMC controller DMA interrupt
39
40  sdon-inverted:
41    type: boolean
42    description: All chips before (not including) WM8505 rev. A2 treated their
43      "clock stop" bit (register offset 0x08 a.k.a. SDMMC_BUSMODE, bit 0x10)
44      as "set 1 to disable SD clock", while all the later versions treated it
45      as "set 0 to disable SD clock". Set this property for later versions of
46      wm,wm8505-sdhc. On wm,wm8650-sdhc and later this property is implied and
47      does not need to be set explicitly
48
49required:
50  - compatible
51  - reg
52  - interrupts
53  - clocks
54
55unevaluatedProperties: false
56
57examples:
58  - |
59    mmc@d800a000 {
60        compatible = "wm,wm8505-sdhc";
61        reg = <0xd800a000 0x1000>;
62        interrupts = <20>, <21>;
63        clocks = <&sdhc>;
64        bus-width = <4>;
65        sdon-inverted;
66    };
67