| /linux/include/dt-bindings/clock/ ! |
| H A D | samsung,s3c64xx-clock.h | 102 #define SCLK_SPI0 90 macro
|
| H A D | exynos7-clk.h | 109 #define SCLK_SPI0 17 macro
|
| H A D | s5pv210.h | 193 #define SCLK_SPI0 171 macro
|
| H A D | rk3188-cru-common.h | 25 #define SCLK_SPI0 69 macro
|
| H A D | rk3128-cru.h | 20 #define SCLK_SPI0 65 macro
|
| H A D | rk3228-cru.h | 18 #define SCLK_SPI0 65 macro
|
| H A D | rv1108-cru.h | 17 #define SCLK_SPI0 65 macro
|
| H A D | rk3308-cru.h | 31 #define SCLK_SPI0 27 macro
|
| H A D | rk3288-cru.h | 20 #define SCLK_SPI0 65 macro
|
| H A D | rk3368-cru.h | 21 #define SCLK_SPI0 65 macro
|
| H A D | rk3399-cru.h | 28 #define SCLK_SPI0 71 macro
|
| /linux/drivers/clk/samsung/ ! |
| H A D | clk-s3c64xx.c | 255 GATE_SCLK(SCLK_SPI0, "sclk_spi0", "dout_spi0", SCLK_GATE, 20),
356 ALIAS(SCLK_SPI0, "s3c6410-spi.0", "spi_busclk2"),
|
| H A D | clk-exynos7.c | 351 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
707 PNAME(mout_sclk_spi0_user_p) = { "fin_pll", "sclk_spi0" };
783 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
|
| H A D | clk-s5pv210.c | 593 GATE(SCLK_SPI0, "sclk_spi0", "dout_spi0", CLK_SRC_MASK0, 16,
|
| H A D | clk-exynos5250.c | 512 GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi_pre0",
|
| /linux/Documentation/devicetree/bindings/clock/ ! |
| H A D | samsung,exynos7-clock.yaml | 155 - const: sclk_spi0
|
| /linux/drivers/clk/rockchip/ ! |
| H A D | clk-rk3128.c | 398 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_3plls_p, 0,
|
| H A D | clk-rk3228.c | 474 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_2plls_p, 0,
|
| H A D | clk-rk3188.c | 391 COMPOSITE_NOMUX(SCLK_SPI0, "sclk_spi0", "pclk_peri", 0,
|
| H A D | clk-rk3368.c | 535 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
|
| H A D | clk-rk3288.c | 516 COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
|
| /linux/arch/arm/boot/dts/rockchip/ ! |
| H A D | rk3xxx.dtsi | 454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
| /linux/arch/arm/boot/dts/samsung/ ! |
| H A D | s5pv210.dtsi | 158 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
|
| /linux/arch/arm64/boot/dts/exynos/ ! |
| H A D | exynos7.dtsi | 238 "sclk_spi0",
|
| /linux/arch/arm64/boot/dts/rockchip/ ! |
| H A D | rk3368.dtsi | 239 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|