Home
last modified time | relevance | path

Searched full:rs1 (Results 1 – 25 of 120) sorted by relevance

12345

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZfh.td204 def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
205 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
267 def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;
269 def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;
270 def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
272 def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
275 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))), (FSGNJN_H $rs1, $rs2)>;
276 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
277 (FSGNJ_H $rs1, (FCVT_H_S $rs2, FRM_DYN))>;
279 // fmadd: rs1 * rs2 + rs3
[all …]
H A DRISCVInstrInfoD.td185 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
186 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
244 def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>;
245 def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>;
252 def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>;
253 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>;
260 def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_S_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
261 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_IN32X FPR32INX:$rs1, FRM_RNE)>;
277 def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>;
279 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
[all …]
H A DRISCVInstrInfoF.td71 def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
72 (any_fma node:$rs1, node:$rs2, node:$rs3), [{
163 (ins GPRMem:$rs1, simm12:$imm12),
164 opcodestr, "$rd, ${imm12}(${rs1})">,
171 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
172 opcodestr, "$rs2, ${imm12}(${rs1})">,
180 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
181 opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
193 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
207 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
[all …]
H A DRISCVGISel.td86 def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
87 (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
90 def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
91 (ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
93 def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
94 def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
95 def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;
102 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
103 (SLTIU GPR:$rs1, simm12:$imm12)>;
104 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
[all …]
H A DRISCVInstrInfoC.td244 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SPMem:$rs1, opnd:$imm),
245 OpcodeStr, "$rd, ${imm}(${rs1})">;
250 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SPMem:$rs1, opnd:$imm),
251 OpcodeStr, "$rs2, ${imm}(${rs1})">;
256 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRCMem:$rs1, opnd:$imm),
257 OpcodeStr, "$rd, ${imm}(${rs1})">;
262 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2,GPRCMem:$rs1, opnd:$imm),
263 OpcodeStr, "$rs2, ${imm}(${rs1})">;
268 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
269 OpcodeStr, "$rs1, $imm"> {
[all …]
H A DRISCVInstrInfoZc.td107 (ins GPRCMem:$rs1, uimm2:$imm),
108 OpcodeStr, "$rd, ${imm}(${rs1})"> {
117 (ins GPRCMem:$rs1, uimm2_lsb0:$imm),
118 OpcodeStr, "$rd, ${imm}(${rs1})"> {
127 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
128 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
137 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
138 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
212 (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
216 def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
[all …]
H A DRISCVInstrInfoZb.td254 : RVInstIUnary<imm12, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
255 opcodestr, "$rd, $rs1">;
261 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
262 "$rd, $rs1, $shamt">;
268 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
269 "$rd, $rs1, $shamt">;
464 def : InstAlias<"ror $rd, $rs1, $shamt",
465 (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
469 def : InstAlias<"rorw $rd, $rs1, $shamt",
470 (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
[all …]
H A DRISCVInstrInfoXwch.td83 (ins GPRCMem:$rs1, uimm5_with_predicate:$imm),
84 "qk.c.lbu", "$rd, ${imm}(${rs1})">,
93 (ins GPRC:$rs2, GPRCMem:$rs1,
95 "qk.c.sb", "$rs2, ${imm}(${rs1})">,
105 (ins GPRCMem:$rs1, uimm6_lsb0:$imm),
106 "qk.c.lhu", "$rd, ${imm}(${rs1})">,
114 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
115 "qk.c.sh", "$rs2, ${imm}(${rs1})">,
124 (ins SPMem:$rs1, uimm4_with_predicate:$imm),
125 "qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,
[all …]
H A DRISCVInstrInfoVSDPatterns.td36 def : Pat<(type (load GPR:$rs1)),
37 (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
40 def : Pat<(store type:$rs2, GPR:$rs1),
41 (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
55 def : Pat<(type (load GPR:$rs1)),
56 (load_instr GPR:$rs1)>;
58 def : Pat<(store type:$rs2, GPR:$rs1),
59 (store_instr reg_class:$rs2, GPR:$rs1)>;
66 def : Pat<(m.Mask (load GPR:$rs1)),
67 (load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL,
[all …]
H A DRISCVInstrInfoZfa.td52 (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
62 let rs1 = imm;
70 (ins rs1ty:$rs1, rtzarg:$frm), opcodestr,
71 "$rd, $rs1$frm"> {
197 def: Pat<(any_frint FPR32:$rs1), (FROUNDNX_S FPR32:$rs1, FRM_DYN)>;
200 def: Pat<(any_fnearbyint FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_DYN)>;
202 def: Pat<(any_fround FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RMM)>;
203 def: Pat<(any_ffloor FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RDN)>;
204 def: Pat<(any_fceil FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RUP)>;
205 def: Pat<(any_ftrunc FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RTZ)>;
[all …]
H A DRISCVInstrInfoXCV.td27 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
28 opcodestr, "$rd, $rs1, $is3, $is2">;
32 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
36 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
55 (ins GPR:$rd, GPR:$rs1, uimm5:$is3, uimm5:$is2),
56 "cv.insert", "$rd, $rs1, $is3, $is2">;
58 (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
59 "cv.insertr", "$rd, $rs1, $rs2">;
74 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
75 opcodestr, "$rd, $rs1, $rs2"> {
[all …]
H A DRISCVInstrInfoXTHead.td68 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
72 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
73 opcodestr, "$vd, $rs1, $vs2$vm"> {
83 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
84 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
94 (ins GPR:$rs1, uimmlog2xlen:$shamt),
95 opcodestr, "$rd, $rs1, $shamt">;
99 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
100 opcodestr, "$rd, $rs1, $msb, $lsb"> {
109 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
[all …]
H A DRISCVInstrInfoSFB.td47 // Conditional binops, that updates update $dst to (op rs1, rs2) when condition
55 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
60 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
65 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
70 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
75 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
80 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
85 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
90 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
96 GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
[all …]
H A DRISCVInstrInfo.td509 (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
510 opcodestr, "$rs1, $rs2, $imm12">,
518 : RVInstI<funct3, OPC_LOAD, (outs GPR:$rd), (ins GPRMem:$rs1, simm12:$imm12),
519 opcodestr, "$rd, ${imm12}(${rs1})">;
523 (ins GPRMemZeroOffset:$rs1), opcodestr, "$rd, $rs1"> {
534 (ins GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
535 opcodestr, "$rs2, ${imm12}(${rs1})">;
539 (ins GPR:$rs2, GPRMemZeroOffset:$rs1),
540 opcodestr, "$rs2, $rs1"> {
547 : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
[all …]
H A DRISCVInstrInfoVVLPatterns.td211 def any_riscv_vfmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
212 [(riscv_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
213 … (riscv_strict_vfmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
214 def any_riscv_vfnmadd_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
215 [(riscv_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
216 … (riscv_strict_vfnmadd_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
217 def any_riscv_vfmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
218 [(riscv_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
219 … (riscv_strict_vfmsub_vl node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl)]>;
220 def any_riscv_vfnmsub_vl : PatFrags<(ops node:$rs1, node:$rs2, node:$rs3, node:$mask, node:$vl),
[all …]
H A DRISCVInstrInfoZfbfmin.td54 def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
55 (FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
56 def : Pat<(riscv_fpextend_bf16 (bf16 FPR16:$rs1)),
57 (FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
68 def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)…
69 def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ…
72 def : Pat<(bf16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
73 def : Pat<(bf16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
79 def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)…
80 def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ…
[all …]
/src/contrib/llvm-project/clang/lib/Headers/
H A Dsifive_vector.h16 #define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \ argument
17 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
18 #define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \ argument
19 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 7, vl)
20 #define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \ argument
21 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 0, vl)
22 #define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \ argument
23 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 1, vl)
24 #define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \ argument
25 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 2, vl)
[all …]
/src/crypto/openssl/crypto/perlasm/
H A Driscv.pm282 # Encoding for aes64ds rd, rs1, rs2 instruction on RV64
283 # XXXXXXX_ rs2 _ rs1 _XXX_ rd _XXXXXXX
286 my $rs1 = read_reg shift;
288 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
292 # Encoding for aes64dsm rd, rs1, rs2 instruction on RV64
293 # XXXXXXX_ rs2 _ rs1 _XXX_ rd _XXXXXXX
296 my $rs1 = read_reg shift;
298 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
302 # Encoding for aes64es rd, rs1, rs2 instruction on RV64
303 # XXXXXXX_ rs2 _ rs1 _XXX_ rd _XXXXXXX
[all …]
/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td299 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
300 (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
302 def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
303 (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
305 def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
306 (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
308 def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
309 (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
312 def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
313 (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2))>;
[all …]
H A DCSKYInstrInfoF1.td308 def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)…
313 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
314 (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
316 def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
317 (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
319 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
320 (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
322 def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
323 (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
326 def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
[all …]
/src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DEmulateInstructionRISCV.cpp168 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) { in CompareB() argument
171 return rs1 == rs2; in CompareB()
173 return rs1 != rs2; in CompareB()
175 return int64_t(rs1) < int64_t(rs2); in CompareB()
177 return int64_t(rs1) >= int64_t(rs2); in CompareB()
179 return rs1 < rs2; in CompareB()
181 return rs1 >= rs2; in CompareB()
221 return transformOptional(inst.rs1.Read(emulator), [&](uint64_t rs1) { in LoadStoreAddr() argument
222 return rs1 + uint64_t(SignExt(inst.imm)); in LoadStoreAddr()
256 return transformOptional(inst.rs1.Read(emulator), in AtomicAddr()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td62 // movr<cond> rs1, rs2, rd
68 // movr<cond> $rs1, $rs2, $rd
69 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),
70 (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
72 // movr<cond> $rs1, $simm10, $rd
73 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),
74 (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
76 // fmovrs<cond> $rs1, $rs2, $rd
77 def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
[all …]
H A DSparcInstrInfo.td408 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
409 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
410 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
413 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
414 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
415 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
423 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
424 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
427 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
428 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
[all …]
H A DSparcInstrVIS.td20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
21 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
26 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
27 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
30 let rd = 0, rs1 = 0, rs2 = 0 in
34 // For VIS Instructions with only rs1, rd operands.
38 (outs RC:$rd), (ins RC:$rs1),
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
42 let rs1 = 0 in
49 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td277 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16),
278 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
281 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16),
282 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"),
293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
294 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
301 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))],
302 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
[all …]

12345