Searched full:qusb2phy_intr_ctrl (Results 1 – 2 of 2) sorted by relevance
53 /* QUSB2PHY_INTR_CTRL register bits */135 QUSB2PHY_INTR_CTRL, enumerator164 [QUSB2PHY_INTR_CTRL] = 0xBC,177 [QUSB2PHY_INTR_CTRL] = 0xbc,206 [QUSB2PHY_INTR_CTRL] = 0x22c,248 [QUSB2PHY_INTR_CTRL] = 0x230,645 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()706 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
111 by the QUSB2PHY_INTR_CTRL register. The required DPSE/112 DMSE configuration is done in QUSB2PHY_INTR_CTRL register