| /linux-6.8/drivers/infiniband/hw/qib/ |
| D | qib_verbs.h | 149 u64 z_unicast_xmit; /* starting count for PMA */
150 u64 z_unicast_rcv; /* starting count for PMA */
151 u64 z_multicast_xmit; /* starting count for PMA */
152 u64 z_multicast_rcv; /* starting count for PMA */
153 u64 z_symbol_error_counter; /* starting count for PMA */
154 u64 z_link_error_recovery_counter; /* starting count for PMA */
155 u64 z_link_downed_counter; /* starting count for PMA */
156 u64 z_port_rcv_errors; /* starting count for PMA */
157 u64 z_port_rcv_remphys_errors; /* starting count for PMA */
158 u64 z_port_xmit_discards; /* starting count for PMA */
[all …]
|
| D | qib_mad.c | 1531 /* Congestion PMA packets start at offset 24 not 64 */ in pma_get_portcounters_cong()
1666 struct qib_pma_counters pma; in pma_get_portcounters_ext() local
1690 qib_snapshot_pmacounters(ibp, &pma); in pma_get_portcounters_ext()
1692 p->port_unicast_xmit_packets = cpu_to_be64(pma.n_unicast_xmit in pma_get_portcounters_ext()
1694 p->port_unicast_rcv_packets = cpu_to_be64(pma.n_unicast_rcv in pma_get_portcounters_ext()
1696 p->port_multicast_xmit_packets = cpu_to_be64(pma.n_multicast_xmit in pma_get_portcounters_ext()
1698 p->port_multicast_rcv_packets = cpu_to_be64(pma.n_multicast_rcv in pma_get_portcounters_ext()
1827 struct qib_pma_counters pma; in pma_set_portcounters_ext() local
1843 qib_snapshot_pmacounters(ibp, &pma); in pma_set_portcounters_ext()
1846 ibp->z_unicast_xmit = pma.n_unicast_xmit; in pma_set_portcounters_ext()
[all …]
|
| /linux-6.8/include/uapi/linux/ |
| D | mdio.h | 40 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
41 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
42 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
49 #define MDIO_PMA_NG_EXTABLE 21 /* 2.5G/5G PMA/PMD extended ability */
70 #define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
71 #define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
73 #define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
84 #define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
160 #define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
191 #define MDIO_PMA_STAT2_LBABLE 0x0001 /* PMA loopback ability */
[all …]
|
| /linux-6.8/drivers/net/phy/ |
| D | phy-c45.c | 14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
62 * genphy_c45_pma_suspend - suspends the PMA module
127 * PMA/PMD type selection is 1.7.5:0 not 1.7.3:0. See 45.2.1.6.1 in genphy_c45_pma_setup_forced()
314 * are controlled through the PMA/PMD MMD registers.
595 * genphy_c45_read_pma - read link speed etc from PMA
645 * genphy_c45_read_mdix - read mdix status from PMA
853 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register in genphy_c45_read_eee_abilities()
885 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
[all …]
|
| D | marvell10g.c | 12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
591 * don't set bit 14 in PMA Extended Abilities (1.11), although they do
594 * the PMA device identifier, with a mask matching models known to have this
602 /* Only some revisions of the 88X3310 family PMA seem to be impacted */ in mv3310_has_pma_ngbaset_quirk()
|
| D | dp83tg720.c | 75 /* PMA/PMD control 1 register (Register 1.0) is present, but it in dp83tg720_read_status()
|
| D | marvell-88x2222.c | 62 /* SFI PMA transmit enable */
69 /* SFI PMA transmit disable */
|
| /linux-6.8/Documentation/devicetree/bindings/phy/ |
| D | samsung,ufs-phy.yaml | 27 - const: phy-pma
101 reg-names = "phy-pma";
|
| D | ti,phy-j721e-wiz.yaml | 79 clock source for the reference clock used in the PHY and PMA digital
147 WIZ node should have subnodes for each of the PMA common refclock
|
| D | cdns,dphy.yaml | 23 - description: PMA state machine clock
|
| /linux-6.8/Documentation/devicetree/bindings/net/ |
| D | xlnx,axi-ethernet.yaml | 100 - description: MGT reference clock (used by optional internal PCS/PMA PHY)
120 description: Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
121 modes, where "pcs-handle" should be used to point to the PCS/PMA PHY,
|
| /linux-6.8/drivers/net/ethernet/aquantia/atlantic/ |
| D | aq_phy.c | 119 /* PMA Standard Device Identifier 2: Address 1.3 */ in aq_phy_init_phy_id()
137 /* PMA Standard Device Identifier: in aq_phy_init()
|
| /linux-6.8/drivers/net/pcs/ |
| D | pcs-xpcs-nxp.c | 67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
153 * Release reset of PMA to enable data flow to/from PCS. in nxp_sja1110_pma_config()
|
| D | pcs-xpcs-wx.c | 148 /* wait pma initialization done */ in txgbe_pma_init_done()
153 dev_err(&xpcs->mdiodev->dev, "xpcs pma initialization timeout\n"); in txgbe_pma_init_done()
|
| /linux-6.8/arch/riscv/include/asm/ |
| D | pgtable-64.h | 118 * 00 - PMA Normal Cacheable, No change to implied PMA memory type
135 * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
|
| D | errata_list.h | 73 * and set the non-0 PMA type if applicable.
|
| /linux-6.8/drivers/net/ethernet/sfc/falcon/ |
| D | qt202x_phy.c | 184 /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD in qt2025c_bug17190_workaround()
186 * persisting for a couple of seconds, we switch PMA/PMD loopback in qt2025c_bug17190_workaround()
203 netif_dbg(efx, hw, efx->net_dev, "bashing QT2025C PMA/PMD\n"); in qt2025c_bug17190_workaround()
284 /* PMA/PMD loopback sets RXIN to inverse polarity and the firmware in qt2025c_select_phy_mode()
|
| D | txc43128_phy.c | 182 /* Reset the PMA/PMD MMD. The documentation is explicit that this does a
211 /* Set PMA to test into loopback using Mt Diablo reg as per app note */ in txc_bist_one()
406 /* Analog register bank in PMA/PMD, PHY XS */ in txc_set_power()
|
| /linux-6.8/drivers/phy/cadence/ |
| D | phy-cadence-sierra.c | 216 /* PHY PMA common registers */
221 /* PHY PMA lane registers */
569 /* PHY PMA lane registers configurations */ in cdns_sierra_phy_init()
581 /* PMA common registers configurations */ in cdns_sierra_phy_init()
591 /* PMA lane registers configurations */ in cdns_sierra_phy_init()
1129 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); in cdns_regmap_init_blocks()
1141 dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n"); in cdns_regmap_init_blocks()
1314 /* PHY PMA lane registers configurations */ in cdns_sierra_phy_configure_multilink()
1326 /* PMA common registers configurations */ in cdns_sierra_phy_configure_multilink()
1336 /* PMA lane registers configurations */ in cdns_sierra_phy_configure_multilink()
[all …]
|
| D | phy-cadence-torrent.c | 168 /* PMA TX Lane registers */
189 /* PMA RX Lane registers */
231 /* PHY PMA common registers */
1206 "timeout waiting for PMA common ready\n"); in cdns_torrent_dp_wait_pma_cmn_ready()
1255 /* PMA lane configuration to deal with multi-link operation */ in cdns_torrent_dp_pma_cmn_rate()
1308 /* PMA common configuration 19.2MHz */ in cdns_torrent_dp_configure_rate()
1311 /* PMA common configuration 25MHz */ in cdns_torrent_dp_configure_rate()
1314 /* PMA common configuration 100MHz */ in cdns_torrent_dp_configure_rate()
1713 * PHY PMA registers configuration functions in cdns_torrent_dp_common_init()
2283 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); in cdns_torrent_regmap_init()
[all …]
|
| /linux-6.8/drivers/phy/rockchip/ |
| D | phy-rockchip-snps-pcie3.c | 94 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3568_init()
138 /* Deassert PCIe PMA output clamp mode */ in rockchip_p3phy_rk3588_init()
|
| /linux-6.8/drivers/infiniband/hw/hfi1/ |
| D | opa_compat.h | 21 /* OPA PMA attribute IDs */
|
| /linux-6.8/include/rdma/ |
| D | ib_pma.h | 14 * PMA class portinfo capability mask bits
|
| /linux-6.8/Documentation/devicetree/bindings/display/bridge/ |
| D | cdns,mhdp8546.yaml | 24 The AUX and PMA registers are not part of this range, they are instead
|
| /linux-6.8/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 158 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
343 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
405 * @pcs_phy: Reference to PCS/PMA PHY if used
|