| /linux-6.8/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
26 with priority below this threshold will not cause the PLIC to raise its
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31 seen while an interrupt handler is active; the PLIC may either queue them or
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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| D | riscv,cpu-intc.txt | 16 via the platform-level interrupt controller (PLIC).
21 entry, though external interrupt controllers (like the PLIC, for example) will
23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| /linux-6.8/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 217 interrupt-parent = <&plic>;
231 plic: interrupt-controller@c000000 { label
232 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
248 interrupt-parent = <&plic>;
299 interrupt-parent = <&plic>;
311 interrupt-parent = <&plic>;
323 interrupt-parent = <&plic>;
335 interrupt-parent = <&plic>;
347 interrupt-parent = <&plic>;
358 interrupt-parent = <&plic>;
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| D | mpfs-icicle-kit-fabric.dtsi | 23 interrupt-parent = <&plic>;
38 interrupt-parent = <&plic>;
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| D | mpfs-m100pfs-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| D | mpfs-polarberry-fabric.dtsi | 26 interrupt-parent = <&plic>;
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| /linux-6.8/arch/riscv/boot/dts/sophgo/ |
| D | cv1800b.dtsi | 12 &plic {
13 compatible = "sophgo,cv1800b-plic", "thead,c900-plic";
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| D | cv1812h.dtsi | 18 &plic {
19 compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
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| D | cv18xx.dtsi | 50 interrupt-parent = <&plic>;
178 plic: interrupt-controller@70000000 { label
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| /linux-6.8/drivers/irqchip/ |
| D | irq-sifive-plic.c | 6 #define pr_fmt(fmt) "plic: " fmt
24 * This driver implements a version of the RISC-V PLIC with the actual layout
29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
190 .name = "SiFive PLIC",
205 .name = "SiFive PLIC",
541 * We can have multiple PLIC instances so setup cpuhp state in __plic_init()
548 "irqchip/sifive/plic:starting", in __plic_init()
578 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
588 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init);
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| D | irq-riscv-intc.c | 55 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
161 * interrupt controllers (such as PLIC, IMSIC and APLIC in riscv_intc_init()
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| /linux-6.8/arch/riscv/boot/dts/allwinner/ |
| D | sun20i-d1s.dtsi | 56 interrupt-parent = <&plic>;
66 plic: interrupt-controller@10000000 { label
67 compatible = "allwinner,sun20i-d1-plic",
68 "thead,c900-plic";
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| /linux-6.8/arch/riscv/boot/dts/renesas/ |
| D | r9a07g043f.dtsi | 51 interrupt-parent = <&plic>;
53 plic: interrupt-controller@12c00000 { label
54 compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
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| /linux-6.8/arch/riscv/boot/dts/starfive/ |
| D | jh7100.dtsi | 146 interrupt-parent = <&plic>;
170 plic: interrupt-controller@c000000 { label
171 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
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| /linux-6.8/arch/riscv/boot/dts/thead/ |
| D | th1520.dtsi | 158 interrupt-parent = <&plic>;
164 plic: interrupt-controller@ffd8000000 { label
165 compatible = "thead,th1520-plic", "thead,c900-plic";
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| /linux-6.8/Documentation/devicetree/bindings/net/can/ |
| D | microchip,mpfs-can.yaml | 43 interrupt-parent = <&plic>;
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| /linux-6.8/Documentation/devicetree/bindings/usb/ |
| D | microchip,mpfs-musb.yaml | 53 interrupt-parent = <&plic>;
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| /linux-6.8/Documentation/devicetree/bindings/spi/ |
| D | microchip,mpfs-spi.yaml | 55 interrupt-parent = <&plic>;
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| /linux-6.8/Documentation/devicetree/bindings/i2c/ |
| D | microchip,corei2c.yaml | 52 interrupt-parent = <&plic>;
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| /linux-6.8/arch/m68k/include/asm/ |
| D | m5272sim.h | 110 #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
111 #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
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| /linux-6.8/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/ |
| D | microarch.json | 62 "BriefDescription": "PLIC arbitration time when the interrupt is not responded",
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| /linux-6.8/arch/powerpc/include/asm/ |
| D | paca.h | 5 * There are some pointers defined that are utilized by PLIC.
70 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
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| /linux-6.8/Documentation/devicetree/bindings/pwm/ |
| D | pwm-sifive.yaml | 69 interrupt-parent = <&plic>;
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| /linux-6.8/Documentation/devicetree/bindings/gpio/ |
| D | sifive,gpio.yaml | 82 interrupt-parent = <&plic>;
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| D | microchip,mpfs-gpio.yaml | 83 interrupt-parent = <&plic>;
|