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/qemu/hw/ide/
H A Dcmd646.c55 static void cmd646_update_irq(PCIDevice *pd);
57 static void cmd646_update_dma_interrupts(PCIDevice *pd) in cmd646_update_dma_interrupts() argument
60 if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) { in cmd646_update_dma_interrupts()
61 pd->config[CFR] |= CFR_INTR_CH0; in cmd646_update_dma_interrupts()
63 pd->config[CFR] &= ~CFR_INTR_CH0; in cmd646_update_dma_interrupts()
66 if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) { in cmd646_update_dma_interrupts()
67 pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1; in cmd646_update_dma_interrupts()
69 pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1; in cmd646_update_dma_interrupts()
73 static void cmd646_update_udma_interrupts(PCIDevice *pd) in cmd646_update_udma_interrupts() argument
76 if (pd->config[CFR] & CFR_INTR_CH0) { in cmd646_update_udma_interrupts()
[all …]
H A Dvia.c125 PCIDevice *pd = PCI_DEVICE(dev); in via_ide_reset() local
126 uint8_t *pci_conf = pd->config; in via_ide_reset()
162 static uint32_t via_ide_cfg_read(PCIDevice *pd, uint32_t addr, int len) in via_ide_cfg_read() argument
164 uint32_t val = pci_default_read_config(pd, addr, len); in via_ide_cfg_read()
165 uint8_t mode = pd->config[PCI_CLASS_PROG]; in via_ide_cfg_read()
185 static void via_ide_cfg_write(PCIDevice *pd, uint32_t addr, in via_ide_cfg_write() argument
188 PCIIDEState *d = PCI_IDE(pd); in via_ide_cfg_write()
190 pci_default_write_config(pd, addr, val, len); in via_ide_cfg_write()
H A Dsii3112.c296 PCIDeviceClass *pd = PCI_DEVICE_CLASS(klass); in sii3112_pci_class_init() local
298 pd->vendor_id = 0x1095; in sii3112_pci_class_init()
299 pd->device_id = 0x3112; in sii3112_pci_class_init()
300 pd->class_id = PCI_CLASS_STORAGE_RAID; in sii3112_pci_class_init()
301 pd->revision = 1; in sii3112_pci_class_init()
302 pd->realize = sii3112_pci_realize; in sii3112_pci_class_init()
H A Dpiix.c109 PCIDevice *pd = PCI_DEVICE(d); in piix_ide_reset() local
110 uint8_t *pci_conf = pd->config; in piix_ide_reset()
/qemu/accel/tcg/
H A Dtb-maint.c78 #define assert_page_locked(pd) tcg_debug_assert(have_mmap_lock()) argument
211 PageDesc *pd; in page_find_alloc() local
238 pd = qatomic_rcu_read(lp); in page_find_alloc()
239 if (pd == NULL) { in page_find_alloc()
246 pd = g_new0(PageDesc, V_L2_SIZE); in page_find_alloc()
248 qemu_spin_init(&pd[i].lock); in page_find_alloc()
251 existing = qatomic_cmpxchg(lp, NULL, pd); in page_find_alloc()
254 qemu_spin_destroy(&pd[i].lock); in page_find_alloc()
256 g_free(pd); in page_find_alloc()
257 pd = existing; in page_find_alloc()
[all …]
/qemu/hw/pci-host/
H A Dq35.c330 PCIDevice *pd = PCI_DEVICE(mch); in mch_update_pam() local
336 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); in mch_update_pam()
344 PCIDevice *pd = PCI_DEVICE(mch); in mch_update_smram() local
345 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); in mch_update_smram()
349 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { in mch_update_smram()
350 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; in mch_update_smram()
351 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; in mch_update_smram()
352 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; in mch_update_smram()
357 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { in mch_update_smram()
368 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { in mch_update_smram()
[all …]
H A Di440fx.c87 PCIDevice *pd = PCI_DEVICE(d); in i440fx_update_memory_mappings() local
92 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); in i440fx_update_memory_mappings()
95 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); in i440fx_update_memory_mappings()
97 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); in i440fx_update_memory_mappings()
/qemu/hw/ipmi/
H A Dpci_ipmi_kcs.c65 static void pci_ipmi_kcs_realize(PCIDevice *pd, Error **errp) in pci_ipmi_kcs_realize() argument
68 PCIIPMIKCSDevice *pik = PCI_IPMI_KCS(pd); in pci_ipmi_kcs_realize()
69 IPMIInterface *ii = IPMI_INTERFACE(pd); in pci_ipmi_kcs_realize()
82 pci_config_set_prog_interface(pd->config, 0x01); /* KCS */ in pci_ipmi_kcs_realize()
83 pci_config_set_interrupt_pin(pd->config, 0x01); in pci_ipmi_kcs_realize()
93 pci_register_bar(pd, 0, PCI_BASE_ADDRESS_SPACE_IO, &pik->kcs.io); in pci_ipmi_kcs_realize()
H A Dpci_ipmi_bt.c66 static void pci_ipmi_bt_realize(PCIDevice *pd, Error **errp) in pci_ipmi_bt_realize() argument
69 PCIIPMIBTDevice *pib = PCI_IPMI_BT(pd); in pci_ipmi_bt_realize()
70 IPMIInterface *ii = IPMI_INTERFACE(pd); in pci_ipmi_bt_realize()
83 pci_config_set_prog_interface(pd->config, 0x02); /* BT */ in pci_ipmi_bt_realize()
84 pci_config_set_interrupt_pin(pd->config, 0x01); in pci_ipmi_bt_realize()
94 pci_register_bar(pd, 0, PCI_BASE_ADDRESS_SPACE_IO, &pib->bt.io); in pci_ipmi_bt_realize()
/qemu/scripts/
H A Dcompare-machine-types.py32 import pandas as pd namespace
253 def get_table(self, req_props: List[Tuple[str, str]]) -> pd.DataFrame:
254 table: List[pd.DataFrame] = []
265 table.append(pd.DataFrame({name: column}))
267 return pd.concat(table, axis=1)
421 def simplify_table(table: pd.DataFrame) -> pd.DataFrame:
441 is_raw: bool) -> pd.DataFrame:
448 table = [pd.DataFrame({'Driver': driver_col}),
449 pd.DataFrame({'Property': prop_col})]
453 df_table = pd.concat(table, axis=1)
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/qemu/hw/display/
H A Dxenfb.c444 void *map, *pd; in xenfb_map_fb() local
448 pd = page->pd; in xenfb_map_fb()
456 * one page directory only, thus pd[1] must be zero. in xenfb_map_fb()
457 * pd[1] of the 32bit struct layout and the lower in xenfb_map_fb()
458 * 32 bits of pd[0] of the 64bit struct layout have in xenfb_map_fb()
464 ptr32 = (void*)page->pd; in xenfb_map_fb()
465 ptr64 = ((void*)page->pd) + 4; in xenfb_map_fb()
467 ptr32 = ((void*)page->pd) - 4; in xenfb_map_fb()
468 ptr64 = (void*)page->pd; in xenfb_map_fb()
473 pd = ptr32; in xenfb_map_fb()
[all …]
/qemu/hw/pci/
H A Dpci_bridge.c168 PCIDevice *pd = PCI_DEVICE(br); in pci_bridge_init_vga_aliases() local
169 uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL); in pci_bridge_init_vga_aliases()
182 pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM], in pci_bridge_init_vga_aliases()
190 PCIDevice *pd = PCI_DEVICE(br); in pci_bridge_region_init() local
191 PCIBus *parent = pci_get_bus(pd); in pci_bridge_region_init()
193 uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND); in pci_bridge_region_init()
219 PCIDevice *pd = PCI_DEVICE(br); in pci_bridge_region_del() local
220 PCIBus *parent = pci_get_bus(pd); in pci_bridge_region_del()
225 pci_unregister_vga(pd); in pci_bridge_region_del()
/qemu/hw/misc/
H A Dimx_ccm.c54 uint32_t pd = 1 + PD(pllreg); /* Pre-divider */ in imx_ccm_calc_pll() local
65 (mfd * pd)) << 10; in imx_ccm_calc_pll()
/qemu/include/hw/xen/interface/io/
H A Dfbif.h128 * Each directory page holds PAGE_SIZE / sizeof(*pd)
130 * PAGE_SIZE / sizeof(*pd) bytes. With PAGE_SIZE == 4096 and
136 unsigned long pd[256]; member
/qemu/hw/scsi/
H A Dmfi.h895 struct mfi_evt_pd pd; member
925 struct mfi_evt_pd pd; member
944 struct mfi_evt_pd pd; member
947 struct mfi_evt_pd pd; member
953 struct mfi_evt_pd pd; member
958 struct mfi_evt_pd pd; member
963 struct mfi_evt_pd pd; member
1244 uint8_t pd; member
1247 } pd[MFI_MAX_ROW_SIZE]; member
H A Dmegasas.c188 "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI", in mfi_frame_desc()
1067 "PD get info std inquiry"); in megasas_pd_get_info_submit()
1073 "PD get info std inquiry", lun); in megasas_pd_get_info_submit()
1085 "PD get info vpd inquiry"); in megasas_pd_get_info_submit()
1089 "PD get info vpd inquiry", lun); in megasas_pd_get_info_submit()
1391 array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id); in megasas_dcmd_cfg_read()
1392 array->pd[0].ref.v.seq_num = 0; in megasas_dcmd_cfg_read()
1393 array->pd[0].fw_state = MFI_PD_STATE_ONLINE; in megasas_dcmd_cfg_read()
1394 array->pd[0].encl.pd = 0xFF; in megasas_dcmd_cfg_read()
1395 array->pd[0].encl.slot = (sdev->id & 0xFF); in megasas_dcmd_cfg_read()
[all …]
/qemu/target/arm/tcg/
H A Dtranslate-sve.c1274 TCGv_i64 pd = tcg_temp_new_i64(); in do_pppp_flags() local
1283 gvec_op->fni8(pd, pn, pm, pg); in do_pppp_flags()
1284 tcg_gen_st_i64(pd, tcg_env, dofs); in do_pppp_flags()
1286 do_predtest1(pd, pg); in do_pppp_flags()
1305 static void gen_and_pg_i64(TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) in gen_and_pg_i64() argument
1307 tcg_gen_and_i64(pd, pn, pm); in gen_and_pg_i64()
1308 tcg_gen_and_i64(pd, pd, pg); in gen_and_pg_i64()
1311 static void gen_and_pg_vec(unsigned vece, TCGv_vec pd, TCGv_vec pn, in gen_and_pg_vec() argument
1314 tcg_gen_and_vec(vece, pd, pn, pm); in gen_and_pg_vec()
1315 tcg_gen_and_vec(vece, pd, pd, pg); in gen_and_pg_vec()
[all …]
/qemu/tests/qtest/
H A Dnpcm7xx_gpio-test.c86 /* PU and PD shouldn't have any impact on DIN. */ in test_dout_to_din()
99 * When output is disabled, and PD is the inverse of PU, PU should be in test_pullup_pulldown()
100 * reflected on DIN. If PD is not the inverse of PU, the state of DIN is in test_pullup_pulldown()
143 * not set. If OTYP is set, DIN is determined by PU/PD. Lower half of in test_open_drain()
144 * DOUT always drives a 0 regardless of OTYP; PU/PD have no effect. When in test_open_drain()
145 * OE is 0, output is determined by PU/PD; OTYP has no effect. in test_open_drain()
H A Dmegasas-test.c89 qos_add_test("dcmd/pd-get-info/fuzz", "megasas", megasas_pd_get_info_fuzz, NULL); in megasas_register_nodes()
/qemu/hw/xen/
H A Dxen_pt_graphics.c175 struct pci_data *pd = NULL; in xen_pt_setup_vga() local
201 pd = (void *)(bios + (unsigned char)rom->pcioffset); in xen_pt_setup_vga()
204 if (pd->device != s->real_device.device_id) { in xen_pt_setup_vga()
205 pd->device = s->real_device.device_id; in xen_pt_setup_vga()
/qemu/hw/ppc/
H A Dprep.c141 uint16_t pd, pd1, pd2; in NVRAM_crc_update() local
144 pd = prev ^ value; in NVRAM_crc_update()
145 pd1 = pd & 0x000F; in NVRAM_crc_update()
146 pd2 = ((pd >> 4) & 0x000F) ^ pd1; in NVRAM_crc_update()
/qemu/migration/
H A Drdma.c338 struct ibv_pd *pd; /* protection domain */ member
888 /* allocate pd */ in qemu_rdma_alloc_pd_cq()
889 rdma->pd = ibv_alloc_pd(rdma->verbs); in qemu_rdma_alloc_pd_cq()
890 if (!rdma->pd) { in qemu_rdma_alloc_pd_cq()
929 if (rdma->pd) { in qemu_rdma_alloc_pd_cq()
930 ibv_dealloc_pd(rdma->pd); in qemu_rdma_alloc_pd_cq()
942 rdma->pd = NULL; in qemu_rdma_alloc_pd_cq()
964 if (rdma_create_qp(rdma->cm_id, rdma->pd, &attr) < 0) { in qemu_rdma_alloc_qp()
993 static void qemu_rdma_advise_prefetch_mr(struct ibv_pd *pd, uint64_t addr, in qemu_rdma_advise_prefetch_mr() argument
1003 ret = ibv_advise_mr(pd, advice, in qemu_rdma_advise_prefetch_mr()
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/qemu/dump/
H A Ddump.c1483 PageDescriptor pd, pd_zero; in write_dump_pages() local
1555 pd.flags = cpu_to_dump32(s, DUMP_DH_COMPRESSED_ZLIB); in write_dump_pages()
1556 pd.size = cpu_to_dump32(s, size_out); in write_dump_pages()
1568 pd.flags = cpu_to_dump32(s, DUMP_DH_COMPRESSED_LZO); in write_dump_pages()
1569 pd.size = cpu_to_dump32(s, size_out); in write_dump_pages()
1582 pd.flags = cpu_to_dump32(s, DUMP_DH_COMPRESSED_SNAPPY); in write_dump_pages()
1583 pd.size = cpu_to_dump32(s, size_out); in write_dump_pages()
1596 pd.flags = cpu_to_dump32(s, 0); in write_dump_pages()
1598 pd.size = cpu_to_dump32(s, size_out); in write_dump_pages()
1609 pd.page_flags = cpu_to_dump64(s, 0); in write_dump_pages()
[all …]
/qemu/include/hw/misc/
H A Dimx_ccm.h20 #define PD(v) (((v) >> 26) & 0xf) macro
/qemu/target/i386/tcg/
H A Demit.c.inc533 * 66 = v*pd Vpd, Hpd, Wps
550 SSEFunc_0_epp ps, pd, fn;
552 pd = s->vex_l ? pd_ymm : pd_xmm;
553 fn = s->prefix & PREFIX_DATA ? pd : ps;
576 * 66 = v*pd Vpd, Hpd, Wps
585 SSEFunc_0_eppp ps, pd, fn;
590 pd = s->vex_l ? pd_ymm : pd_xmm;
591 fn = s->prefix & PREFIX_DATA ? pd : ps;
667 /* PS maps to the DQ integer instruction, PD maps to QDQ. */ \
718 * 66 = v*pd Vpd, Hpd, Wpd
[all …]

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