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/qemu/docs/devel/
H A Dcodebase.rst15 `MAINTAINERS <https://gitlab.com/qemu-project/qemu/-/blob/master/MAINTAINERS>`_
48 * `accel <https://gitlab.com/qemu-project/qemu/-/tree/master/accel>`_:
53 `target <https://gitlab.com/qemu-project/qemu/-/tree/master/target>`_.
54 * `audio <https://gitlab.com/qemu-project/qemu/-/tree/master/audio>`_:
56 * `authz <https://gitlab.com/qemu-project/qemu/-/tree/master/authz>`_:
58 * `backends <https://gitlab.com/qemu-project/qemu/-/tree/master/backends>`_:
61 * `block <https://gitlab.com/qemu-project/qemu/-/tree/master/block>`_:
63 * `bsd-user <https://gitlab.com/qemu-project/qemu/-/tree/master/bsd-user>`_:
67 * `chardev <https://gitlab.com/qemu-project/qemu/-/tree/master/chardev>`_:
69 * `common-user <https://gitlab.com/qemu-project/qemu/-/tree/master/common-user>`_:
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H A Dsubmitting-a-pull-request.rst61 **Pull requests not for master should say "not for master" and have
64 string "not for master" in the cover letter email, and make sure the
67 pull requests that should be applied to master.
H A Dqapi-domain.rst6 <https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html>`_
10 <https://www.sphinx-doc.org/en/master/usage/domains/python.html>`_
16 <https://www.sphinx-doc.org/en/master/usage/domains/index.html>`_
21 <https://www.sphinx-doc.org/en/master/usage/extensions/autodoc.html>`_
64 <https://www.sphinx-doc.org/en/master/usage/restructuredtext/basics.html#field-lists>`_
66 <https://www.sphinx-doc.org/en/master/usage/domains/python.html#info-field-lists>`_
352 <https://www.sphinx-doc.org/en/master/usage/restructuredtext/roles.html>`_
355 <https://www.sphinx-doc.org/en/master/usage/domains/python.html#cross-referencing-python-objects>`_.
358 <https://www.sphinx-doc.org/en/master/usage/referencing.html#role-any>`_
401 <https://www.sphinx-doc.org/en/master/usage/domains/python.html#target-specification>`_,
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/qemu/io/
H A Dchannel-tls.c37 ret = qio_channel_write(tioc->master, buf, len, errp); in qio_channel_tls_write_handler()
54 ret = qio_channel_read(tioc->master, buf, len, errp); in qio_channel_tls_read_handler()
65 qio_channel_tls_new_server(QIOChannel *master, in qio_channel_tls_new_server() argument
76 tioc->master = master; in qio_channel_tls_new_server()
77 ioc->follow_coroutine_ctx = master->follow_coroutine_ctx; in qio_channel_tls_new_server()
78 if (qio_channel_has_feature(master, QIO_CHANNEL_FEATURE_SHUTDOWN)) { in qio_channel_tls_new_server()
81 object_ref(OBJECT(master)); in qio_channel_tls_new_server()
99 trace_qio_channel_tls_new_server(tioc, master, creds, aclname); in qio_channel_tls_new_server()
108 qio_channel_tls_new_client(QIOChannel *master, in qio_channel_tls_new_client() argument
119 tioc->master = master; in qio_channel_tls_new_client()
[all …]
H A Dchannel-websock.c493 ret = qio_channel_read(ioc->master, in qio_channel_websock_handshake_read()
539 ret = qio_channel_write(wioc->master, in qio_channel_websock_handshake_send()
601 wioc->master, in qio_channel_websock_handshake_io()
678 qio_channel_shutdown(ioc->master, QIO_CHANNEL_SHUTDOWN_BOTH, NULL); in qio_channel_websock_write_close()
850 qio_channel_shutdown(ioc->master, QIO_CHANNEL_SHUTDOWN_BOTH, NULL); in qio_channel_websock_decode_payload()
877 qio_channel_websock_new_server(QIOChannel *master) in qio_channel_websock_new_server() argument
885 wioc->master = master; in qio_channel_websock_new_server()
886 ioc->follow_coroutine_ctx = master->follow_coroutine_ctx; in qio_channel_websock_new_server()
887 if (qio_channel_has_feature(master, QIO_CHANNEL_FEATURE_SHUTDOWN)) { in qio_channel_websock_new_server()
890 object_ref(OBJECT(master)); in qio_channel_websock_new_server()
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H A Dtrace-events40 …channel_tls_new_client(void *ioc, void *master, void *creds, const char *hostname) "TLS new client…
41 …_channel_tls_new_server(void *ioc, void *master, void *creds, const char *aclname) "TLS new client…
56 qio_channel_websock_new_server(void *ioc, void *master) "Websock new client ioc=%p master=%p"
/qemu/tests/unit/
H A Dtest-crypto-secret.c393 Object *master = object_new_with_props( in test_secret_crypt_raw() local
396 "master", in test_secret_crypt_raw()
409 "keyid", "master", in test_secret_crypt_raw()
419 object_unparent(master); in test_secret_crypt_raw()
426 Object *master = object_new_with_props( in test_secret_crypt_base64() local
429 "master", in test_secret_crypt_base64()
441 "keyid", "master", in test_secret_crypt_base64()
451 object_unparent(master); in test_secret_crypt_base64()
458 Object *master = object_new_with_props( in test_secret_crypt_short_key() local
461 "master", in test_secret_crypt_short_key()
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/qemu/
H A D.gitpublish7 base = master
12 base = master
18 base = master
24 base = master
30 base = master
36 base = master
42 base = master
48 base = master
/qemu/hw/intc/
H A Di8259_common.c92 ISADevice *i8259_init_chip(const char *name, ISABus *bus, bool master) in i8259_init_chip() argument
99 qdev_prop_set_uint32(dev, "iobase", master ? 0x20 : 0xa0); in i8259_init_chip()
100 qdev_prop_set_uint32(dev, "elcr_addr", master ? 0x4d0 : 0x4d1); in i8259_init_chip()
101 qdev_prop_set_uint8(dev, "elcr_mask", master ? 0xf8 : 0xde); in i8259_init_chip()
102 qdev_prop_set_bit(dev, "master", master); in i8259_init_chip()
123 if (s->master) { in pic_get_statistics()
141 s->master ? 0 : 1, s->irr, s->imr, s->isr, in pic_print_info()
200 DEFINE_PROP_BIT("master", PICCommonState, master, 0, false),
214 * wiring of the slave to the master is hard-coded in device model in pic_common_class_init()
H A Dslavio_intctl.c43 * There is a system master controller and one for each cpu.
54 struct SLAVIO_INTCTLState *master; member
121 slavio_check_interrupts(s->master, 1); in slavio_intctl_mem_writel()
127 slavio_check_interrupts(s->master, 1); in slavio_intctl_mem_writel()
145 // master system interrupt controller
412 g_string_append_printf(buf, "master: pending 0x%08x, disabled 0x%08x\n", in slavio_intctl_print_info()
426 "master-interrupt-controller", INTCTLM_SIZE); in slavio_intctl_init()
440 s->slaves[i].master = s; in slavio_intctl_init()
H A Di8259.c85 master, the IRQ coming from the slave is not taken into account in pic_get_irq()
91 if (s->special_fully_nested_mode && s->master) { in pic_get_irq()
110 trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add); in pic_update_irq()
122 int irq_index = s->master ? irq : irq + 8; in pic_set_irq()
124 trace_pic_set_irq(s->master, irq, level); in pic_set_irq()
236 trace_pic_ioport_write(s->master, addr, val); in pic_ioport_write()
347 trace_pic_ioport_read(s->master, addr, ret); in pic_ioport_read()
/qemu/include/hw/misc/
H A Dtz-msc.h2 * ARM TrustZone master security controller emulation
13 * This is a model of the TrustZone master security controller (MSC).
18 * The MSC sits in front of a device which can be a bus master (such as
20 * pass through or reject transactions made by that bus master.
34 * + Named GPIO input "cfg_nonsec": set to 1 if the bus master should be
40 * + Property "downstream": MemoryRegion defining where bus master transactions
46 * this should be passed to the bus master device as the region it should
/qemu/docs/system/
H A Dsecrets.rst113 A single master key can be used to encrypt all subsequent secrets, **but it is
136 and also encryption with a master key:
146 It is recommended for production deployments to use a master key secret, and
147 then pass all subsequent inline secrets encrypted with the master key.
149 Each QEMU instance must have a distinct master key, and that must be generated
150 from a cryptographically secure random data source. The master key should be
151 deleted immediately upon QEMU shutdown. If passing the master key as a file,
154 keyring can be used to pass the master key to QEMU.
157 with this master key.
162 The only item that needs strongly protecting is the master key file.
/qemu/include/io/
H A Dchannel-tls.h39 * technical restriction on which type of master channel is
48 QIOChannel *master; member
68 * @master: the underlying channel object
86 * master channel
91 qio_channel_tls_new_server(QIOChannel *master,
98 * @master: the underlying channel object
116 * master channel
121 qio_channel_tls_new_client(QIOChannel *master,
H A Dchannel-websock.h45 * technical restriction on which type of master channel is
57 QIOChannel *master; member
72 * @master: the underlying channel object
83 * master channel
88 qio_channel_websock_new_server(QIOChannel *master);
/qemu/hw/ppc/
H A Dpnv_chiptod.c11 * There is a master chip TOD, which sends signals to slave chip TODs to
45 #define TOD_M_PATH_CTRL_REG 0x00000000 /* Master Path ctrl reg */
53 /* -- TOD primary/secondary master/slave control register -- */
56 /* -- TOD primary/secondary master/slave status register -- */
116 * master, does not support errors, etc. in pnv_chiptod_xscom_read()
119 val |= PPC_BIT(12); /* Primary config master path select */ in pnv_chiptod_xscom_read()
124 val |= PPC_BIT(26); /* Is using master path select */ in pnv_chiptod_xscom_read()
127 val |= PPC_BIT(23); /* Is active master */ in pnv_chiptod_xscom_read()
129 val |= PPC_BIT(24); /* Is backup master */ in pnv_chiptod_xscom_read()
131 val |= PPC_BIT(25); /* Is slave (should backup master set this?) */ in pnv_chiptod_xscom_read()
[all …]
/qemu/crypto/
H A Dblock-luks.c692 * Given a key slot, user password, and the master key,
693 * will store the encrypted master key there, and update the
770 * Generate a key that we'll use to encrypt the master in qcrypto_block_luks_store_key()
787 * master key material in qcrypto_block_luks_store_key()
807 * Before storing the master key, we need to vastly in qcrypto_block_luks_store_key()
823 * Now we encrypt the split master key with the key generated in qcrypto_block_luks_store_key()
835 /* Write out the slot's master key material. */ in qcrypto_block_luks_store_key()
865 * the master encryption key from the key slot.
907 * decrypt the master key - we just blindly assume in qcrypto_block_luks_load_key()
921 * We need to read the master key material from the in qcrypto_block_luks_load_key()
[all …]
H A Dblock-luks-priv.h121 /* master key checksum after PBKDF2 */
124 /* salt for master key PBKDF2 */
127 /* iterations for master key PBKDF2 */
/qemu/docs/system/devices/
H A Divshmem.rst41 With device property ``master=on``, the guest will copy the shared
42 memory on migration to the destination host. With ``master=off``, the
47 At most one of the devices sharing the same memory can be master. The
48 master must complete migration before you plug back the other devices.
/qemu/docs/specs/
H A Dfsi.rst6 master/slave and the end engine.
32 3. The FSI master: A controller in the platform service processor (e.g. BMC)
39 integration of the FSI master IP with the OPB, mainly the existence of an
89 dev: fsi.master, id ""
100 dev: fsi.master, id ""
/qemu/.gitlab-ci.d/
H A Dcheck-patch.py25 # ancestor between the user's branch and current git master.
27 subprocess.check_call(["git", "fetch", "--refetch", "check-patch", "master"])
30 "check-patch/master", "HEAD"],
H A Dcheck-dco.py24 subprocess.check_call(["git", "fetch", "--refetch", "check-dco", "master"])
27 "check-dco/master", "HEAD"],
90 git rebase -i master -x 'git commit --amend --no-edit -s'
/qemu/docs/system/riscv/
H A Dshakti-c.rst11 https://gitlab.com/shaktiproject/cores/shakti-soc/-/blob/master/fpga/boards/artya7-100t/c-class/REA…
53 $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/sdk/shakti_sdk_qemu.zip
71 $ wget -c https://gitlab.com/behindbytes/shakti-binaries/-/raw/master/dts/shakti.dtb
/qemu/include/hw/fsi/
H A Dfsi-master.h5 * IBM Flexible Service Interface Master
15 #define TYPE_FSI_MASTER "fsi.master"
/qemu/hw/misc/
H A Dtz-msc.c2 * ARM TrustZone master security controller emulation
76 * Check whether to allow an access from the bus master, returning in tz_msc_check()
91 * whether bus master is configured as Secure or NonSecure in tz_msc_check()
102 /* Access to Secure region by Secure bus master: OK */ in tz_msc_check()
106 /* Attempted access to Secure region by NS bus master: block */ in tz_msc_check()

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