Searched full:mt7988 (Results 1 – 25 of 29) sorted by relevance
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| /linux-6.8/Documentation/devicetree/bindings/clock/ |
| D | mediatek,mt7988-ethwarp.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
7 title: MediaTek MT7988 ethwarp Controller
13 The Mediatek MT7988 ethwarp controller provides clocks and resets for the
14 Ethernet related subsystems found the MT7988 SoC.
20 - const: mediatek,mt7988-ethwarp
47 compatible = "mediatek,mt7988-ethwarp";
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| D | mediatek,mt7988-xfi-pll.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
7 title: MediaTek MT7988 XFI PLL Clock Controller
18 const: mediatek,mt7988-xfi-pll
43 compatible = "mediatek,mt7988-xfi-pll";
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| D | mediatek,topckgen.yaml | 40 - mediatek,mt7988-mcusys
41 - mediatek,mt7988-topckgen
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| D | mediatek,ethsys.yaml | 25 - mediatek,mt7988-ethsys
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| D | mediatek,apmixedsys.yaml | 25 - mediatek,mt7988-apmixedsys
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| /linux-6.8/drivers/clk/mediatek/ |
| D | clk-mt7988-eth.c | 16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
17 #include <dt-bindings/reset/mediatek,mt7988-resets.h>
131 { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
132 { .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
133 { .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
134 { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
141 .name = "clk-mt7988-eth",
149 MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
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| D | clk-mt7988-xfipll.c | 13 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
66 { .compatible = "mediatek,mt7988-xfi-pll", .data = &xfipll_desc },
73 .name = "clk-mt7988-xfipll",
81 MODULE_DESCRIPTION("MediaTek MT7988 XFI PLL clock driver");
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| D | clk-mt7988-apmixed.c | 17 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
75 { .compatible = "mediatek,mt7988-apmixedsys" },
109 .name = "clk-mt7988-apmixed",
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| D | Makefile | 65 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
66 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
67 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
68 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
69 obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
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| D | clk-mt7988-infracfg.c | 16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
261 { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
268 .name = "clk-mt7988-infracfg",
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| D | clk-mt7988-topckgen.c | 16 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
310 { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
311 { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
320 .name = "clk-mt7988-topckgen",
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| D | Kconfig | 427 tristate "Clock driver for MediaTek MT7988"
432 This driver supports MediaTek MT7988 basic clocks and clocks
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| /linux-6.8/Documentation/devicetree/bindings/net/pcs/ |
| D | mediatek,sgmiisys.yaml | 30 - mediatek,mt7988-sgmiisys0
31 - mediatek,mt7988-sgmiisys1
50 const: mediatek,mt7988-sgmii
79 - mediatek,mt7988-sgmiisys0
80 - mediatek,mt7988-sgmiisys1
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| /linux-6.8/drivers/net/dsa/ |
| D | Kconfig | 45 MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
66 in the MediaTek MT7988 SoC.
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| D | mt7530-mmio.c | 14 { .compatible = "mediatek,mt7988-switch", .data = &mt753x_table[ID_MT7988], },
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| /linux-6.8/Documentation/devicetree/bindings/sound/ |
| D | mediatek,mt7986-afe.yaml | 19 - mediatek,mt7988-afe
108 const: mediatek,mt7988-afe
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| /linux-6.8/Documentation/devicetree/bindings/net/dsa/ |
| D | mediatek,mt7530.yaml | 23 The MT7988 SoC comes with a built-in switch similar to MT7531 as well as four
92 Built-in switch of the MT7988 SoC
93 const: mediatek,mt7988-switch
287 const: mediatek,mt7988-switch
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| /linux-6.8/Documentation/devicetree/bindings/soc/mediatek/ |
| D | mediatek,mt7986-wo-ccif.yaml | 23 - mediatek,mt7988-wo-ccif
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| /linux-6.8/Documentation/devicetree/bindings/arm/mediatek/ |
| D | mediatek,infracfg.yaml | 33 - mediatek,mt7988-infracfg
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| D | mediatek,mt7622-wed.yaml | 25 - mediatek,mt7988-wed
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| /linux-6.8/Documentation/devicetree/bindings/watchdog/ |
| D | mediatek,mtk-wdt.yaml | 28 - mediatek,mt7988-wdt
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| /linux-6.8/Documentation/devicetree/bindings/thermal/ |
| D | mediatek,lvts-thermal.yaml | 21 - mediatek,mt7988-lvts-ap
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| /linux-6.8/Documentation/devicetree/bindings/net/ |
| D | mediatek,net.yaml | 27 - mediatek,mt7988-eth
333 const: mediatek,mt7988-eth
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| /linux-6.8/drivers/net/phy/ |
| D | mediatek-ge-soc.c | 728 /* TrFreeze = 0 (mt7988 default) */ in mt798x_phy_common_finetune()
840 /* VgaDecRate is 1 at default on mt7988 */ in mt7988_phy_finetune()
1405 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, in mt7988_phy_probe_shared()
1516 .name = "MediaTek MT7988 PHY",
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| D | Kconfig | 266 the MT7981 and MT7988 SoCs. These PHYs need calibration data
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