| /linux-5.10/drivers/dma/ |
| D | img-mdc-dma.c | 118 struct mdc_dma *mdma; member
149 static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg) in mdc_readl() argument
151 return readl(mdma->regs + reg); in mdc_readl()
154 static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg) in mdc_writel() argument
156 writel(val, mdma->regs + reg); in mdc_writel()
161 return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg); in mdc_chan_readl()
166 mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg); in mdc_chan_writel()
181 static inline struct device *mdma2dev(struct mdc_dma *mdma) in mdma2dev() argument
183 return mdma->dma_dev.dev; in mdma2dev()
210 struct mdc_dma *mdma = mchan->mdma; in mdc_list_desc_config() local
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| D | mpc512x_dma.c | 256 struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan); in mpc_dma_execute() local
300 memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd)); in mpc_dma_execute()
303 mdma->tcd[cid].e_sg = 1; in mpc_dma_execute()
305 if (mdma->is_mpc8308) { in mpc_dma_execute()
307 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
310 out_8(&mdma->regs->dmaserq, cid); in mpc_dma_execute()
313 out_8(&mdma->regs->dmassrt, cid); in mpc_dma_execute()
318 static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off) in mpc_dma_irq_process() argument
327 mchan = &mdma->channels[ch + off]; in mpc_dma_irq_process()
331 out_8(&mdma->regs->dmacint, ch + off); in mpc_dma_irq_process()
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| D | stm32-mdma.c | 8 * Driver for STM32 MDMA controller
35 /* MDMA Generic getter/setter */
42 #define STM32_MDMA_GISR0 0x0000 /* MDMA Int Status Reg 1 */
43 #define STM32_MDMA_GISR1 0x0004 /* MDMA Int Status Reg 2 */
45 /* MDMA Channel x interrupt/status register */
54 /* MDMA Channel x interrupt flag clear register */
67 /* MDMA Channel x error status register */
76 /* MDMA Channel x control register */
97 /* MDMA Channel x transfer configuration register */
151 /* MDMA Channel x block number of data register */
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| D | Makefile | 72 obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
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| D | Kconfig | 567 Enable support for the on-chip MDMA controller on STMicroelectronics
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| /linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | st,stm32-mdma.yaml | 4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
7 title: STMicroelectronics STM32 MDMA Controller bindings
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
12 DMA clients connected to the STM32 MDMA controller must use the format
14 a phandle to the MDMA controller plus the following five integer cells:
43 0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
44 0x1: Each MDMA request triggers a block transfer (max 64K bytes)
45 0x2: Each MDMA request triggers a repeated block transfer
46 0x3: Each MDMA request triggers a linked list transfer
48 if no HW ack signal is used by the MDMA client
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| /linux-5.10/drivers/ata/ |
| D | pata_pdc2027x.c | 92 { 0xdf, 0x5f }, /* MDMA mode 0 */
93 { 0x6b, 0x27 }, /* MDMA mode 1 */
94 { 0x69, 0x25 }, /* MDMA mode 2 */
368 /* Set the MDMA timing registers with value table for 133MHz */ in pdc2027x_set_dmamode()
371 PDPRINTK("Set mdma regs... \n"); in pdc2027x_set_dmamode()
379 PDPRINTK("Set mdma regs done\n"); in pdc2027x_set_dmamode()
381 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode); in pdc2027x_set_dmamode()
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| D | pata_mpc52xx.c | 79 /* ATAPI-4 MDMA specs (in clocks) */
212 u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
213 u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
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| D | pata_macio.c | 64 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
110 * and MDMA, I think I've figured the format of the timing register,
166 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
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| D | pata_ep93xx.c | 98 /* MDMA Operation Register */
106 /* PIO/MDMA/UDMA Data Registers */
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| /linux-5.10/drivers/dma/qcom/ |
| D | hidma.c | 117 struct hidma_dev *mdma = to_hidma_dev(ddev); in hidma_process_completed() local
141 llstat = hidma_ll_status(mdma->lldev, mdesc->tre_ch); in hidma_process_completed()
405 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memcpy() local
420 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memcpy()
438 struct hidma_dev *mdma = mchan->dmadev; in hidma_prep_dma_memset() local
453 hidma_ll_set_transfer_params(mdma->lldev, mdesc->tre_ch, in hidma_prep_dma_memset()
533 struct hidma_dev *mdma = mchan->dmadev; in hidma_free_chan_resources() local
548 hidma_ll_free(mdma->lldev, mdesc->tre_ch); in hidma_free_chan_resources()
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| /linux-5.10/drivers/rapidio/devices/ |
| D | tsi721.c | 113 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); in tsi721_maint_dma()
125 bd_ptr = priv->mdma.bd_base; in tsi721_maint_dma()
153 priv->mdma.ch_id, ch_stat); in tsi721_maint_dma()
1433 priv->mdma.ch_id = TSI721_DMACH_MAINT; in tsi721_bdma_maint_init()
1443 priv->mdma.bd_num = bd_num; in tsi721_bdma_maint_init()
1444 priv->mdma.bd_phys = bd_phys; in tsi721_bdma_maint_init()
1445 priv->mdma.bd_base = bd_ptr; in tsi721_bdma_maint_init()
1462 priv->mdma.bd_base = NULL; in tsi721_bdma_maint_init()
1466 priv->mdma.sts_phys = sts_phys; in tsi721_bdma_maint_init()
1467 priv->mdma.sts_base = sts_ptr; in tsi721_bdma_maint_init()
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| D | tsi721.h | 889 struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */ member
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| /linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | ti,omap-iommu.txt | 28 instance number should be 0 for DSP MDMA MMUs and 1 for
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| /linux-5.10/drivers/ide/ |
| D | pmac.c | 85 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
132 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
134 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
180 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
636 * Calculate MDMA timings for all cells
694 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n", in set_timings_mdma()
722 /* Clear out mdma bits and disable udma */ in set_timings_mdma()
768 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", in set_timings_mdma()
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| D | cs5530.c | 70 * UDMA/MDMA. It has to be one or the other, for the pair, though
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| D | sc1200.c | 97 * UDMA/MDMA. It has to be one or the other, for the pair, though
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| /linux-5.10/include/dt-bindings/clock/ |
| D | stm32mp1-clks.h | 113 #define MDMA 100 macro
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| /linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos5433-clock.txt | 23 which generates clocks for G2D/MDMA IPs.
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| /linux-5.10/arch/arm/boot/dts/ |
| D | stm32h743.dtsi | 348 compatible = "st,stm32h7-mdma";
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| D | exynos5250.dtsi | 710 mdma0: mdma@10800000 {
721 mdma1: mdma@11c10000 {
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| D | exynos4210-universal_c210.dts | 632 mdma0: mdma@12840000 {
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| D | exynos5420.dtsi | 470 mdma0: mdma@10800000 {
481 mdma1: mdma@11c10000 {
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| D | s5pv210.dtsi | 532 mdma1: mdma@fa200000 {
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| /linux-5.10/drivers/crypto/stm32/ |
| D | stm32-hash.c | 409 struct scatterlist *sg, int length, int mdma) in stm32_hash_xmit_dma() argument
433 if (mdma) in stm32_hash_xmit_dma()
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