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/linux/Documentation/devicetree/bindings/net/
H A Dloongson,ls1b-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1b-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1B Gigabit Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1B Gigabit Ethernet MAC Controller is based on
17 - Dual 10/100/1000Mbps GMAC controllers
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
19 - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
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/linux/Documentation/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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/linux/arch/mips/include/asm/mach-loongson64/
H A Dkernel-entry-init.h7 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
28 /* Loongson-3A R4+ */
31 beq t1, t2, 1f
33 /* Loongson-3A R2/R3 */
38 1:
59 /* Loongson-3A R4+ */
62 beq t1, t2, 1f
64 /* Loongson-3A R2/R3 */
69 1:
89 beq s0, (PRID_IMP_LOONGSON_64C | PRID_REV_LOONGSON3B_R1), 1f
[all …]
H A Dloongson.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 /* machine-specific boot configuration */
40 /* machine-specific reboot/halt operation */
49 /* loongson-specific command line, env and memory initialization */
77 #define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
81 #define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
85 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
88 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
89 /* Loongson-3 specific registers */
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/linux/Documentation/devicetree/bindings/mips/loongson/
H A Ddevices.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson based Platforms
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
12 Devices with a Loongson CPU shall have the following properties.
20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
24 - description: Classic Loongson64 Quad Core + RS780E
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/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
12 LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`参考文献 <loongarch-references-zh_CN>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
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/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dintroduction.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
12 LoongArch是一種新的RISC ISA，在一定程度上類似於MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`參考文獻 <loongarch-references-zh_TW>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 參數寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 臨時寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 靜態寄存器 是
[all …]
/linux/arch/loongarch/kernel/
H A Dlbt.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Author: Qi Hu <huqi@loongson.cn>
4 * Huacai Chen <chenhuacai@loongson.cn>
6 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
10 #include <asm/asm-extable.h>
11 #include <asm/asm-offsets.h>
82 EX st.d t1, a0, (1 * SCR_REG_WIDTH)
102 EX ld.d t1, a0, (1 * SCR_REG_WIDTH)
133 la.pcrel a0, 1f
136 1:
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H A Dgenex.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
30 * reprogramming. Fall through -- see handle_vint() below -- and have
48 bne t0, t1, 1f
50 1: move a0, sp
59 b cache_parity_error
89 SYM_DATA(unwind_hint_\exception, .word 668b - 666b)
/linux/arch/loongarch/power/
H A Dhibernate_asm.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Author: Huacai Chen <chenhuacai@loongson.cn>
6 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
10 #include <asm/asm-offsets.h>
30 b swsusp_save
41 1:
46 bne t1, t3, 1b
48 bnez t0, 0b
/linux/drivers/gpio/
H A Dgpio-loongson.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-2F/3A/3B GPIO Support
6 * Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
20 #include <loongson.h>
99 struct device *dev = &pdev->dev; in loongson_gpio_probe()
103 return -ENOMEM; in loongson_gpio_probe()
105 gc->label = "loongson-gpio-chip"; in loongson_gpio_probe()
106 gc->base = 0; in loongson_gpio_probe()
107 gc->ngpio = LOONGSON_N_GPIO; in loongson_gpio_probe()
108 gc->get = loongson_gpio_get_value; in loongson_gpio_probe()
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-loongson1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Loongson-1 DWMAC glue layer
5 * Copyright (C) 2011-2023 Keguang Zhang <keguang.zhang@gmail.com>
21 /* Loongson-1 SYSCON Registers */
25 /* Loongson-1B SYSCON Register Bits */
34 #define GMAC1_USE_PWM23 BIT(1)
37 /* Loongson-1C SYSCON Register Bits */
59 struct ls1x_dwmac *dwmac = plat_dat->bsp_priv; in ls1b_dwmac_setup()
64 /* This shouldn't fail - stmmac_get_platform_resources() in ls1b_dwmac_setup()
67 dev_err(&pdev->dev, "Could not get IO_MEM resources\n"); in ls1b_dwmac_setup()
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/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include <dt-bindings/interrupt-controller/irq.h>
8 compatible = "loongson,loongson2k1000";
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "loongson,gs264";
21 #clock-cells = <1>;
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H A Dloongson64c-package.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/irq.h>
6 #address-cells = <2>;
7 #size-cells = <2>;
9 cpuintc: interrupt-controller {
10 #address-cells = <0>;
11 #interrupt-cells = <1>;
12 interrupt-controller;
13 compatible = "mti,cpu-interrupt-controller";
16 package0: bus@1fe00000 {
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023 Loongson Technology Corporation Limited
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
[all …]
/linux/arch/loongarch/include/asm/
H A Dbitrev.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
14 asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(__swab32(x))); in __arch_bitrev32()
22 asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(__swab16(x))); in __arch_bitrev16()
30 asm("bitrev.4b %0, %1" : "=r"(ret) : "r"(x)); in __arch_bitrev8()
H A Dfutex.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
10 #include <asm/asm-extable.h>
17 "1: ll.w %1, %4 # __futex_atomic_op\n" \
20 " beqz $t0, 1b \n" \
22 _ASM_EXTABLE_UACCESS_ERR(1b, 3b, %0) \
23 _ASM_EXTABLE_UACCESS_ERR(2b, 3b, %0) \
42 __futex_atomic_op("add.w $t0, %1, %z5", ret, oldval, uaddr, oparg); in arch_futex_atomic_op_inuser()
45 __futex_atomic_op("or $t0, %1, %z5", ret, oldval, uaddr, oparg); in arch_futex_atomic_op_inuser()
48 __futex_atomic_op("and $t0, %1, %z5", ret, oldval, uaddr, ~oparg); in arch_futex_atomic_op_inuser()
[all …]
H A Dloongson.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Author: Huacai Chen <chenhuacai@loongson.cn>
4 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
21 #define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
22 #define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1)
26 #define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
29 #define LOONGSON_REG_SIZE 0x00100000 /* 1M */
30 #define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
32 /* GPIO Regs - r/w */
47 " ld.b $zero, %[hw], 0 \n" in xconf_writel()
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H A Dkvm_pch_pic.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2024 Loongson Technology Corporation Limited
44 uint64_t mask; /* 1:disable irq, 0:enable irq */
45 uint64_t htmsi_en; /* 1:msi */
46 uint64_t edge; /* 1:edge triggered, 0:level triggered */
47 uint64_t auto_ctrl0; /* only use default value 00b */
48 uint64_t auto_ctrl1; /* only use default value 00b */
52 uint64_t polarity; /* 0: high level trigger, 1: low level trigger */
/linux/arch/mips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
34 select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
145 bool "Generic board-agnostic MIPS kernel"
287 Build a generic DT-based kernel image that boots on select
288 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
380 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
381 DECstation porting pages on <http://decstation.unix-ag.org/>.
445 Olivetti M700-10 workstations.
482 bool "Loongson 32-bit family of machines"
485 This enables support for the Loongson-1 family of machines.
[all …]
/linux/arch/loongarch/lib/
H A Dunaligned.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
10 #include <asm/asm-extable.h>
15 li.w a0, -EFAULT
30 addi.d t0, a2, -1
35 1: ld.b t3, a0, 0
36 b 3f
41 addi.d t1, t1, -8
42 addi.d a0, a0, -1
43 addi.d a2, a2, -1
[all …]
H A Dmemset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 #include <asm/alternative-asm.h>
26 ALTERNATIVE "b __memset_generic", \
27 "b __memset_fast", CPU_FEATURE_UAL
48 1: st.b a1, a0, 0
49 addi.d a0, a0, 1
50 addi.d a2, a2, -1
51 bgt a2, zero, 1b
79 addi.d a4, a2, -64
[all …]
H A Dmemmove.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7 #include <asm/alternative-asm.h>
32 ALTERNATIVE "b __rmemcpy_generic", \
33 "b __rmemcpy_fast", CPU_FEATURE_UAL
51 1: ld.b t0, a1, -1
52 st.b t0, a0, -1
53 addi.d a0, a0, -1
54 addi.d a1, a1, -1
55 addi.d a2, a2, -1
[all …]
/linux/arch/mips/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
[all …]
/linux/arch/loongarch/mm/
H A Dpage.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
13 lu12i.w t0, 1 << (PAGE_SHIFT - 12)
15 1:
25 st.d zero, a0, -64
26 st.d zero, a0, -56
27 st.d zero, a0, -48
28 st.d zero, a0, -40
29 st.d zero, a0, -32
30 st.d zero, a0, -24
[all …]

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