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/linux-6.8/drivers/mailbox/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
58 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
84 This driver provides support for inter-processor communication
85 between CPU cores and MCU processor on Some Rockchip SOCs.
172 module will be called mailbox-mpfs.
181 providing an interface for invoking the inter-process communication
182 signals from the application processor to other masters.
194 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
197 An implementation of the APM X-Gene Interprocessor Communication
[all …]
/linux-6.8/drivers/firmware/tegra/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 IVC (Inter-VM Communication) protocol is part of the IPC
9 (Inter Processor Communication) framework on Tegra. It maintains the
19 BPMP (Boot and Power Management Processor) is designed to off-loading
/linux-6.8/tools/perf/pmu-events/arch/x86/amdzen4/
Ddata-fabric.json4 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 0.",
12 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 1.",
20 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 2.",
28 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 3.",
36 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 4.",
44 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 5.",
52 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 6.",
60 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 7.",
68 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 8.",
76 … "PublicDescription": "Read data beats (64 bytes) for local processor at Coherent Station (CS) 9.",
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/linux-6.8/Documentation/devicetree/bindings/mailbox/
Dqcom-ipcc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
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Dmtk,adsp-mbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
16 signal the other processor using interrupts.
21 - mediatek,mt8195-adsp-mbox
22 - mediatek,mt8186-adsp-mbox
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Dxlnx,zynqmp-ipi-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
14 +-------------------------------------+
16 +-------------------------------------+
17 +--------------------------------------------------+
18 TF-A | |
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/linux-6.8/Documentation/devicetree/bindings/powerpc/nintendo/
Dwii.txt11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
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/linux-6.8/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/linux-6.8/Documentation/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
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/linux-6.8/arch/arc/kernel/
Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
29 #include <asm/processor.h>
54 return -EINVAL; in arc_get_cpu_map()
57 return -EINVAL; in arc_get_cpu_map()
64 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
70 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
71 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
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/linux-6.8/drivers/media/pci/cx18/
Dcx18-scb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "cx18-mailbox.h"
14 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
65 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 /* Offset where to find the Inter-Processor Communication data */
96 /* These fields form Inter-Processor Communication data which is used
102 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
/linux-6.8/Documentation/translations/zh_CN/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
30 +-----+ +---------+ +-------+
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/linux-6.8/Documentation/translations/zh_TW/arch/loongarch/
Dirq-chip-model.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
30 +-----+ +---------+ +-------+
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/linux-6.8/Documentation/devicetree/bindings/misc/
Dqcom,fastrpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 The FastRPC implements an IPC (Inter-Processor Communication)
16 to offload tasks to the DSP and free up the application processor for
25 - adsp
26 - mdsp
27 - sdsp
28 - cdsp
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/linux-6.8/drivers/media/platform/mediatek/vcodec/encoder/
Dvenc_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * struct venc_vpu_inst - encoder VPU driver instance
23 * @id: the id of inter-processor interrupt
/linux-6.8/include/linux/remoteproc/
Dmtk_scp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * enum ipi_id - the id of inter-processor interrupt
/linux-6.8/arch/mips/kernel/
Dsmp-up.c6 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
14 * Send inter-processor interrupt
58 return -ENOSYS; in up_cpu_disable()
/linux-6.8/Documentation/virt/kvm/devices/
Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
56 * Current processor priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
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/linux-6.8/Documentation/userspace-api/media/
Dglossary.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
45 **Digital Signal Processor**
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
101 **Image Signal Processor**
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/linux-6.8/drivers/media/platform/mediatek/vpu/
Dmtk_vpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
15 * VPU (video processor unit) is a tiny processor controlling video hardware
25 * enum ipi_id - the id of inter-processor interrupt
67 * enum rst_id - reset id to register reset function for VPU watchdog timeout
82 * vpu_ipi_register - register an ipi function
98 * vpu_ipi_send - send data from AP to vpu.
105 * This function is thread-safe. When this function returns,
117 * vpu_get_plat_device - get VPU's platform device
128 * vpu_wdt_reg_handler - register a VPU watchdog handler
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/linux-6.8/Documentation/devicetree/bindings/media/
Dmediatek,mdp3-rdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8195-mdp3-rdma
27 - mediatek,mt8195-vdo1-rdma
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/linux-6.8/sound/soc/intel/avs/
Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
41 /* SKL Intel HD Audio Inter-Processor Communication Registers */
60 #define AVS_FW_REG_BASE(adev) ((adev)->spec->sram_base_offset)
67 /* DSP -> HOST communication window */
69 /* HOST -> DSP communication window */
75 ((adev)->spec->sram_base_offset + \
76 (adev)->spec->sram_window_size * (window_idx))
79 ((adev)->dsp_ba + avs_sram_offset(adev, window_idx))
/linux-6.8/sound/soc/intel/skylake/
Dcnl-sst-dsp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2016-17, Intel Corporation.
21 /* Intel HD Audio Inter-Processor Communication Registers */
67 #define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1)
69 /* core reset - asserted high */
73 /* core run/stall - when set to 1 core is stalled */
77 /* set power active - when set to 1 turn core on */
81 /* current power active - power status of cores, set by hardware */
/linux-6.8/arch/powerpc/platforms/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
37 bool "ePAPR para-virtualization support"
39 Enables ePAPR para-virtualization support for guests.
48 a hypervisor. This option is not user-selectable but should
65 bool "Device-tree based CPU feature discovery & setup"
124 registers are used for inter-processor communication.
206 bool "On-chip CPU temperature sensor support"
209 G3 and G4 processors have an on-chip temperature sensor called the
210 'Thermal Assist Unit (TAU)', which, in theory, can measure the on-die
211 temperature within 2-4 degrees Celsius. This option shows the current
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/linux-6.8/drivers/media/platform/verisilicon/
Dhantro_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 #include <linux/v4l2-controls.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-vp9.h>
16 #include <media/videobuf2-core.h>
51 * struct hantro_aux_buf - auxiliary DMA buffer for hardware data
103 * @dpb_longterm: DPB long-term
186 * @reference_mode: inter prediction type
188 * @interpolation_filter: filter selection for inter prediction
220 * @tile_r_info: per-tile information array
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